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(Updated June 16, 2015, 11:15 p.m.) Review request for Default. Repository: gem5 Description (updated) ------- Changeset 10875:cd40bfae3fd1 --------------------------- cpu: implements vector registers This patch aims at adding vector registers type. The type is defined as a std::array of some fixed number of uint64_ts. The isa_parser.py has been modified to parse vector register operands and generate the required code. Different cpus have vector register files now. Diffs (updated) ----- src/arch/SConscript ebb3d0737aa7 src/arch/alpha/isa.hh ebb3d0737aa7 src/arch/alpha/registers.hh ebb3d0737aa7 src/arch/arm/insts/static_inst.cc ebb3d0737aa7 src/arch/arm/isa.hh ebb3d0737aa7 src/arch/arm/registers.hh ebb3d0737aa7 src/arch/isa_parser.py ebb3d0737aa7 src/arch/mips/isa.hh ebb3d0737aa7 src/arch/mips/registers.hh ebb3d0737aa7 src/arch/null/registers.hh ebb3d0737aa7 src/arch/power/isa.hh ebb3d0737aa7 src/arch/power/registers.hh ebb3d0737aa7 src/arch/sparc/isa.hh ebb3d0737aa7 src/arch/sparc/registers.hh ebb3d0737aa7 src/arch/x86/insts/static_inst.cc ebb3d0737aa7 src/arch/x86/isa.hh ebb3d0737aa7 src/arch/x86/registers.hh ebb3d0737aa7 src/cpu/StaticInstFlags.py ebb3d0737aa7 src/cpu/base_dyn_inst.hh ebb3d0737aa7 src/cpu/checker/cpu.hh ebb3d0737aa7 src/cpu/checker/cpu_impl.hh ebb3d0737aa7 src/cpu/checker/thread_context.hh ebb3d0737aa7 src/cpu/exec_context.hh ebb3d0737aa7 src/cpu/minor/dyn_inst.cc ebb3d0737aa7 src/cpu/minor/exec_context.hh ebb3d0737aa7 src/cpu/minor/scoreboard.cc ebb3d0737aa7 src/cpu/o3/O3CPU.py ebb3d0737aa7 src/cpu/o3/cpu.hh ebb3d0737aa7 src/cpu/o3/cpu.cc ebb3d0737aa7 src/cpu/o3/dyn_inst.hh ebb3d0737aa7 src/cpu/o3/free_list.hh ebb3d0737aa7 src/cpu/o3/regfile.hh ebb3d0737aa7 src/cpu/o3/regfile.cc ebb3d0737aa7 src/cpu/o3/rename_map.hh ebb3d0737aa7 src/cpu/o3/thread_context.hh ebb3d0737aa7 src/cpu/o3/thread_context_impl.hh ebb3d0737aa7 src/cpu/reg_class.hh ebb3d0737aa7 src/cpu/simple/base.hh ebb3d0737aa7 src/cpu/simple_thread.hh ebb3d0737aa7 src/cpu/static_inst.hh ebb3d0737aa7 src/cpu/thread_context.hh ebb3d0737aa7 src/sim/insttracer.hh ebb3d0737aa7 Diff: http://reviews.gem5.org/r/2828/diff/ Testing ------- Thanks, Nilay Vaish _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
