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src/cpu/o3/fetch_impl.hh (lines 331 - 355) <http://reviews.gem5.org/r/2855/#comment5569> This is doing almost exactly the same thing as resetStage(). Is there any way you could refactor it to remove this duplication? - Andreas Sandberg On May 28, 2015, 4:39 p.m., Alexandru Dutu wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2855/ > ----------------------------------------------------------- > > (Updated May 28, 2015, 4:39 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10861:2a0f7f75fe9c > --------------------------- > cpu: o3: Fetch stage updates for hw threads priority list > This patch makes sure the priority_list in the fetch stage is kept in sync > with suspendContext and activateContext calls. > > > Diffs > ----- > > src/cpu/o3/cpu.cc d02b45a554b52c68cce41e1b3895fb8582a639dd > src/cpu/o3/fetch.hh d02b45a554b52c68cce41e1b3895fb8582a639dd > src/cpu/o3/fetch_impl.hh d02b45a554b52c68cce41e1b3895fb8582a639dd > > Diff: http://reviews.gem5.org/r/2855/diff/ > > > Testing > ------- > > Quick regressions passed for all ISAs. > > > Thanks, > > Alexandru Dutu > > _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
