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(Updated April 13, 2016, 7:53 p.m.) Review request for Default. Changes ------- Set correct base. (Apologies, missed the -o flag.) Repository: gem5 Description ------- Add support for McVerSi memory consistency verification framework This patch implements the Gem5-specific portion of McVerSi (a framework for simulation-based memory consistency verification) [1]. Currently, only the O3CPU is supported. [1] http://ac.marcoelver.com/research/mcversi Diffs (updated) ----- src/arch/arm/isa/formats/aarch64.isa df24b9af42c7 src/arch/arm/isa/formats/m5ops.isa df24b9af42c7 src/arch/arm/isa/insts/m5ops.isa df24b9af42c7 src/cpu/o3/commit_impl.hh df24b9af42c7 src/cpu/o3/dyn_inst.hh df24b9af42c7 src/cpu/o3/dyn_inst_impl.hh df24b9af42c7 src/cpu/o3/lsq_unit_impl.hh df24b9af42c7 src/sim/SConscript df24b9af42c7 src/sim/mcversi.hh PRE-CREATION src/sim/mcversi.cc PRE-CREATION src/sim/pseudo_inst.hh df24b9af42c7 src/sim/pseudo_inst.cc df24b9af42c7 util/m5/m5op.h df24b9af42c7 util/m5/m5op_x86.S df24b9af42c7 util/m5/m5ops.h df24b9af42c7 Diff: http://reviews.gem5.org/r/3449/diff/ Testing ------- Unless explicitly enabled (via loading appropriate workload), this is component is unused. However, bugs have been found elsewhere in Gem5 by McVerSi (which is its purpose!). (I will not restate them here to keep the discussion on topic.) Thanks, Marco Elver _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
