----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3449/ -----------------------------------------------------------
(Updated May 20, 2016, 11:45 a.m.) Review request for Default. Repository: gem5 Description ------- Add support for McVerSi memory consistency verification framework This patch implements the Gem5-specific portion of McVerSi (a framework for simulation-based memory consistency verification) [1]. Architectures supported are: - ARM (current mc2lib code generation only supports ARMv7). - X86 (pseudo ops available via mmapped IPR interface). Currently, only the O3CPU is supported. [1] http://ac.marcoelver.com/research/mcversi Diffs (updated) ----- src/arch/arm/isa/formats/m5ops.isa 54cf9a388a9d src/cpu/o3/lsq_unit_impl.hh 54cf9a388a9d src/cpu/o3/dyn_inst_impl.hh 54cf9a388a9d src/cpu/o3/dyn_inst.hh 54cf9a388a9d src/cpu/o3/commit_impl.hh 54cf9a388a9d src/arch/arm/isa/insts/m5ops.isa 54cf9a388a9d src/sim/pseudo_inst.hh 54cf9a388a9d src/sim/mcversi.cc PRE-CREATION src/sim/mcversi.hh PRE-CREATION src/sim/SConscript 54cf9a388a9d util/m5/m5ops.h 54cf9a388a9d util/m5/m5op.h 54cf9a388a9d util/m5/m5op_x86.S 54cf9a388a9d src/sim/pseudo_inst.cc 54cf9a388a9d src/arch/arm/isa/formats/aarch64.isa 54cf9a388a9d Diff: http://reviews.gem5.org/r/3449/diff/ Testing ------- Unless explicitly enabled (via loading appropriate workload), this component is unused. Tested with ARM+Classic and X86+Ruby. Precompiled workloads that were used for testing available here: http://ac.marcoelver.com/res/mcversi_guest_workload_gem5.tar.gz However, bugs have been found elsewhere in Gem5 while testing McVerSi (see http://www.mail-archive.com/[email protected]/msg18940.html , and 1 of 2 bugs from paper http://reviews.gem5.org/r/2842/ ). (I will not restate them here to keep the discussion on topic.) Thanks, Marco Elver _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
