> On May 7, 2016, 2:34 p.m., Andreas Hansson wrote: > >
Thank you for your comments! As I want to avoid making changes hastily, I expect to be able to start addressing these in about 1-2 weeks time earliest. - Marco ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3449/#review8290 ----------------------------------------------------------- On May 5, 2016, 1:11 p.m., Marco Elver wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3449/ > ----------------------------------------------------------- > > (Updated May 5, 2016, 1:11 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Add support for McVerSi memory consistency verification framework > > This patch implements the Gem5-specific portion of McVerSi (a framework for > simulation-based memory consistency verification) [1]. > > Architectures supported are: > - ARM (current mc2lib code generation only supports ARMv7). > - X86 (pseudo ops available via mmapped IPR interface). > > Currently, only the O3CPU is supported. > > [1] http://ac.marcoelver.com/research/mcversi > > > Diffs > ----- > > src/arch/arm/isa/formats/aarch64.isa df24b9af42c7 > src/arch/arm/isa/formats/m5ops.isa df24b9af42c7 > src/arch/arm/isa/insts/m5ops.isa df24b9af42c7 > src/cpu/o3/commit_impl.hh df24b9af42c7 > src/cpu/o3/dyn_inst.hh df24b9af42c7 > src/cpu/o3/dyn_inst_impl.hh df24b9af42c7 > src/cpu/o3/lsq_unit_impl.hh df24b9af42c7 > src/sim/SConscript df24b9af42c7 > src/sim/mcversi.hh PRE-CREATION > src/sim/mcversi.cc PRE-CREATION > src/sim/pseudo_inst.hh df24b9af42c7 > src/sim/pseudo_inst.cc df24b9af42c7 > util/m5/m5op.h df24b9af42c7 > util/m5/m5op_x86.S df24b9af42c7 > util/m5/m5ops.h df24b9af42c7 > > Diff: http://reviews.gem5.org/r/3449/diff/ > > > Testing > ------- > > Unless explicitly enabled (via loading appropriate workload), this component > is unused. > > Tested with ARM+Classic and X86+Ruby. Precompiled workloads that were used > for testing available here: > http://ac.marcoelver.com/res/mcversi_guest_workload_gem5.tar.gz > > However, bugs have been found elsewhere in Gem5 while testing McVerSi (see > http://www.mail-archive.com/[email protected]/msg18940.html , and 1 of 2 bugs > from paper http://reviews.gem5.org/r/2842/ ). (I will not restate them here > to keep the discussion on topic.) > > > Thanks, > > Marco Elver > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
