Eden Avivi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33494 )
Change subject: misc: Master/Slave terminology
......................................................................
misc: Master/Slave terminology
Changed QueuedMasterPort and QueuedSlavePort
Change-Id: I7d84d0df3d0003a3447c7118abcbba43443b3b23
---
M src/dev/arm/smmu_v3_ports.cc
M src/dev/arm/smmu_v3_ports.hh
M src/dev/x86/intdev.hh
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/coherent_xbar.cc
M src/mem/coherent_xbar.hh
M src/mem/dram_ctrl.cc
M src/mem/dram_ctrl.hh
M src/mem/mem_delay.cc
M src/mem/mem_delay.hh
M src/mem/noncoherent_xbar.cc
M src/mem/noncoherent_xbar.hh
M src/mem/qos/mem_sink.cc
M src/mem/qos/mem_sink.hh
M src/mem/qport.hh
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
M src/mem/snoop_filter.hh
M src/mem/token_port.cc
M src/mem/tport.cc
M src/mem/tport.hh
M src/mem/xbar.hh
23 files changed, 58 insertions(+), 55 deletions(-)
diff --git a/src/dev/arm/smmu_v3_ports.cc b/src/dev/arm/smmu_v3_ports.cc
index 3f54250..e950f56 100644
--- a/src/dev/arm/smmu_v3_ports.cc
+++ b/src/dev/arm/smmu_v3_ports.cc
@@ -80,7 +80,7 @@
SMMUv3SlaveInterface &_ifc,
PortID _id)
:
- QueuedSlavePort(_name, &_ifc, respQueue, _id),
+ QueuedResponsePort(_name, &_ifc, respQueue, _id),
ifc(_ifc),
respQueue(_ifc, *this)
{}
@@ -138,7 +138,7 @@
SMMUATSMasterPort::SMMUATSMasterPort(const std::string &_name,
SMMUv3SlaveInterface &_ifc) :
- QueuedMasterPort(_name, &_ifc, reqQueue, snoopRespQueue),
+ QueuedRequestPort(_name, &_ifc, reqQueue, snoopRespQueue),
ifc(_ifc),
reqQueue(_ifc, *this),
snoopRespQueue(_ifc, *this)
@@ -152,7 +152,7 @@
SMMUATSSlavePort::SMMUATSSlavePort(const std::string &_name,
SMMUv3SlaveInterface &_ifc) :
- QueuedSlavePort(_name, &_ifc, respQueue),
+ QueuedResponsePort(_name, &_ifc, respQueue),
ifc(_ifc),
respQueue(_ifc, *this)
{}
diff --git a/src/dev/arm/smmu_v3_ports.hh b/src/dev/arm/smmu_v3_ports.hh
index ee68bbb..a8bf84e 100644
--- a/src/dev/arm/smmu_v3_ports.hh
+++ b/src/dev/arm/smmu_v3_ports.hh
@@ -71,7 +71,7 @@
virtual ~SMMUMasterTableWalkPort() {}
};
-class SMMUSlavePort : public QueuedSlavePort
+class SMMUSlavePort : public QueuedResponsePort
{
protected:
SMMUv3SlaveInterface &ifc;
@@ -106,7 +106,7 @@
virtual ~SMMUControlPort() {}
};
-class SMMUATSMasterPort : public QueuedMasterPort
+class SMMUATSMasterPort : public QueuedRequestPort
{
protected:
SMMUv3SlaveInterface &ifc;
@@ -120,7 +120,7 @@
virtual ~SMMUATSMasterPort() {}
};
-class SMMUATSSlavePort : public QueuedSlavePort
+class SMMUATSSlavePort : public QueuedResponsePort
{
protected:
SMMUv3SlaveInterface &ifc;
diff --git a/src/dev/x86/intdev.hh b/src/dev/x86/intdev.hh
index a681a2e..815406a 100644
--- a/src/dev/x86/intdev.hh
+++ b/src/dev/x86/intdev.hh
@@ -94,7 +94,7 @@
}
template <class Device>
-class IntMasterPort : public QueuedMasterPort
+class IntMasterPort : public QueuedRequestPort
{
private:
ReqPacketQueue reqQueue;
@@ -115,7 +115,7 @@
public:
IntMasterPort(const std::string& _name, SimObject* _parent,
Device* dev, Tick _latency) :
- QueuedMasterPort(_name, _parent, reqQueue, snoopRespQueue),
+ QueuedRequestPort(_name, _parent, reqQueue, snoopRespQueue),
reqQueue(*_parent, *this), snoopRespQueue(*_parent, *this),
device(dev), latency(_latency)
{
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 0187703..71eab09 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -66,7 +66,7 @@
BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
BaseCache *_cache,
const std::string &_label)
- : QueuedSlavePort(_name, _cache, queue),
+ : QueuedResponsePort(_name, _cache, queue),
queue(*_cache, *this, true, _label),
blocked(false), mustSendRetry(false),
sendRetryEvent([this]{ processSendRetry(); }, _name)
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index c129661..176a7e5 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -119,7 +119,7 @@
* and the sendDeferredPacket of the timing port is modified to
* consider both the transmit list and the requests from the MSHR.
*/
- class CacheMasterPort : public QueuedMasterPort
+ class CacheMasterPort : public QueuedRequestPort
{
public:
@@ -139,7 +139,7 @@
CacheMasterPort(const std::string &_name, BaseCache *_cache,
ReqPacketQueue &_reqQueue,
SnoopRespPacketQueue &_snoopRespQueue) :
- QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue)
+ QueuedRequestPort(_name, _cache, _reqQueue, _snoopRespQueue)
{ }
/**
@@ -241,7 +241,7 @@
* incoming requests. If blocked, the port will issue a retry once
* unblocked.
*/
- class CacheSlavePort : public QueuedSlavePort
+ class CacheSlavePort : public QueuedResponsePort
{
public:
diff --git a/src/mem/coherent_xbar.cc b/src/mem/coherent_xbar.cc
index c5778fb..e64df9e 100644
--- a/src/mem/coherent_xbar.cc
+++ b/src/mem/coherent_xbar.cc
@@ -94,7 +94,7 @@
// create the slave ports, once again starting at zero
for (int i = 0; i < p->port_slave_connection_count; ++i) {
std::string portName = csprintf("%s.slave[%d]", name(), i);
- QueuedSlavePort* bp = new CoherentXBarSlavePort(portName, *this,
i);
+ QueuedResponsePort* bp = new CoherentXBarSlavePort(portName,
*this, i);
slavePorts.push_back(bp);
respLayers.push_back(new RespLayer(*bp, *this,
csprintf("respLayer%d", i)));
@@ -685,7 +685,7 @@
void
CoherentXBar::forwardTiming(PacketPtr pkt, PortID exclude_slave_port_id,
- const std::vector<QueuedSlavePort*>& dests)
+ const std::vector<QueuedResponsePort*>& dests)
{
DPRINTF(CoherentXBar, "%s for %s\n", __func__, pkt->print());
@@ -915,7 +915,7 @@
std::pair<MemCmd, Tick>
CoherentXBar::forwardAtomic(PacketPtr pkt, PortID exclude_slave_port_id,
PortID source_master_port_id,
- const std::vector<QueuedSlavePort*>& dests)
+ const std::vector<QueuedResponsePort*>& dests)
{
// the packet may be changed on snoops, record the original
// command to enable us to restore it between snoops so that
diff --git a/src/mem/coherent_xbar.hh b/src/mem/coherent_xbar.hh
index 300fc0c..09d81ca 100644
--- a/src/mem/coherent_xbar.hh
+++ b/src/mem/coherent_xbar.hh
@@ -82,7 +82,7 @@
* be instantiated for each of the master ports connecting to the
* crossbar.
*/
- class CoherentXBarSlavePort : public QueuedSlavePort
+ class CoherentXBarSlavePort : public QueuedResponsePort
{
private:
@@ -97,7 +97,7 @@
CoherentXBarSlavePort(const std::string &_name,
CoherentXBar &_xbar, PortID _id)
- : QueuedSlavePort(_name, &_xbar, queue, _id), xbar(_xbar),
+ : QueuedResponsePort(_name, &_xbar, queue, _id), xbar(_xbar),
queue(_xbar, *this)
{ }
@@ -209,14 +209,14 @@
private:
/** The port which we mirror internally. */
- QueuedSlavePort& slavePort;
+ QueuedResponsePort& slavePort;
public:
/**
* Create a snoop response port that mirrors a given slave port.
*/
- SnoopRespPort(QueuedSlavePort& slave_port, CoherentXBar& _xbar) :
+ SnoopRespPort(QueuedResponsePort& slave_port, CoherentXBar&
_xbar) :
RequestPort(slave_port.name() + ".snoopRespPort", &_xbar),
slavePort(slave_port) { }
@@ -247,7 +247,7 @@
std::vector<SnoopRespPort*> snoopRespPorts;
- std::vector<QueuedSlavePort*> snoopPorts;
+ std::vector<QueuedResponsePort*> snoopPorts;
/**
* Store the outstanding requests that we are expecting snoop
@@ -324,7 +324,7 @@
* @param dests Vector of destination ports for the forwarded pkt
*/
void forwardTiming(PacketPtr pkt, PortID exclude_slave_port_id,
- const std::vector<QueuedSlavePort*>& dests);
+ const std::vector<QueuedResponsePort*>& dests);
Tick recvAtomicBackdoor(PacketPtr pkt, PortID slave_port_id,
MemBackdoorPtr *backdoor=nullptr);
@@ -362,7 +362,8 @@
std::pair<MemCmd, Tick> forwardAtomic(PacketPtr pkt,
PortID exclude_slave_port_id,
PortID source_master_port_id,
- const
std::vector<QueuedSlavePort*>&
+ const std::
+ vector<QueuedResponsePort*>&
dests);
/** Function called by the port when the crossbar is recieving a
Functional
diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index 5f0fcc7..54f5b15 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -2960,7 +2960,7 @@
}
DRAMCtrl::MemoryPort::MemoryPort(const std::string& name, DRAMCtrl&
_memory)
- : QueuedSlavePort(name, &_memory, queue), queue(_memory, *this, true),
+ : QueuedResponsePort(name, &_memory, queue), queue(_memory, *this,
true),
memory(_memory)
{ }
diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh
index 0fe78da..a8433c8 100644
--- a/src/mem/dram_ctrl.hh
+++ b/src/mem/dram_ctrl.hh
@@ -92,9 +92,9 @@
private:
- // For now, make use of a queued slave port to avoid dealing with
+ // For now, make use of a queued response port to avoid dealing with
// flow control for the responses being sent back
- class MemoryPort : public QueuedSlavePort
+ class MemoryPort : public QueuedResponsePort
{
RespPacketQueue queue;
diff --git a/src/mem/mem_delay.cc b/src/mem/mem_delay.cc
index 9b4e7b6..f4ebcce 100644
--- a/src/mem/mem_delay.cc
+++ b/src/mem/mem_delay.cc
@@ -78,7 +78,7 @@
}
MemDelay::RequestPort::RequestPort(const std::string &_name, MemDelay
&_parent)
- : QueuedMasterPort(_name, &_parent,
+ : QueuedRequestPort(_name, &_parent,
_parent.reqQueue, _parent.snoopRespQueue),
parent(_parent)
{
@@ -126,7 +126,7 @@
MemDelay::ResponsePort::
ResponsePort(const std::string &_name, MemDelay &_parent)
- : QueuedSlavePort(_name, &_parent, _parent.respQueue),
+ : QueuedResponsePort(_name, &_parent, _parent.respQueue),
parent(_parent)
{
}
diff --git a/src/mem/mem_delay.hh b/src/mem/mem_delay.hh
index d337b3d..46414c5 100644
--- a/src/mem/mem_delay.hh
+++ b/src/mem/mem_delay.hh
@@ -71,7 +71,7 @@
Port &getPort(const std::string &if_name,
PortID idx=InvalidPortID) override;
- class RequestPort : public QueuedMasterPort
+ class RequestPort : public QueuedRequestPort
{
public:
RequestPort(const std::string &_name, MemDelay &_parent);
@@ -97,7 +97,7 @@
MemDelay& parent;
};
- class ResponsePort : public QueuedSlavePort
+ class ResponsePort : public QueuedResponsePort
{
public:
ResponsePort(const std::string &_name, MemDelay &_parent);
diff --git a/src/mem/noncoherent_xbar.cc b/src/mem/noncoherent_xbar.cc
index 47be023..8ec668a 100644
--- a/src/mem/noncoherent_xbar.cc
+++ b/src/mem/noncoherent_xbar.cc
@@ -79,7 +79,8 @@
// create the slave ports, once again starting at zero
for (int i = 0; i < p->port_slave_connection_count; ++i) {
std::string portName = csprintf("%s.slave[%d]", name(), i);
- QueuedSlavePort* bp = new NoncoherentXBarSlavePort(portName,
*this, i);
+ QueuedResponsePort* bp =
+ new NoncoherentXBarSlavePort(portName, *this, i);
slavePorts.push_back(bp);
respLayers.push_back(new RespLayer(*bp, *this,
csprintf("respLayer%d", i)));
diff --git a/src/mem/noncoherent_xbar.hh b/src/mem/noncoherent_xbar.hh
index 1d3541c..4249649 100644
--- a/src/mem/noncoherent_xbar.hh
+++ b/src/mem/noncoherent_xbar.hh
@@ -79,7 +79,7 @@
* will be instantiated for each of the master ports connecting to
* the crossbar.
*/
- class NoncoherentXBarSlavePort : public QueuedSlavePort
+ class NoncoherentXBarSlavePort : public QueuedResponsePort
{
private:
@@ -93,7 +93,7 @@
NoncoherentXBarSlavePort(const std::string &_name,
NoncoherentXBar &_xbar, PortID _id)
- : QueuedSlavePort(_name, &_xbar, queue, _id), xbar(_xbar),
+ : QueuedResponsePort(_name, &_xbar, queue, _id), xbar(_xbar),
queue(_xbar, *this)
{ }
diff --git a/src/mem/qos/mem_sink.cc b/src/mem/qos/mem_sink.cc
index 1f104e4..24c41c3 100644
--- a/src/mem/qos/mem_sink.cc
+++ b/src/mem/qos/mem_sink.cc
@@ -344,7 +344,8 @@
MemSinkCtrl::MemoryPort::MemoryPort(const std::string& n,
MemSinkCtrl& m)
- : QueuedSlavePort(n, &m, queue, true), memory(m), queue(memory, *this,
true)
+ : QueuedResponsePort(n, &m, queue, true),
+ memory(m), queue(memory, *this, true)
{}
AddrRangeList
diff --git a/src/mem/qos/mem_sink.hh b/src/mem/qos/mem_sink.hh
index 9a51269..3f7622f 100644
--- a/src/mem/qos/mem_sink.hh
+++ b/src/mem/qos/mem_sink.hh
@@ -64,7 +64,7 @@
using PacketQueue = std::deque<PacketPtr>;
private:
- class MemoryPort : public QueuedSlavePort
+ class MemoryPort : public QueuedResponsePort
{
private:
/** reference to parent memory object */
diff --git a/src/mem/qport.hh b/src/mem/qport.hh
index 97a2065..4ba6c58 100644
--- a/src/mem/qport.hh
+++ b/src/mem/qport.hh
@@ -55,7 +55,7 @@
* queue is a parameter to allow tailoring of the queue implementation
* (used in the cache).
*/
-class QueuedSlavePort : public ResponsePort
+class QueuedResponsePort : public ResponsePort
{
protected:
@@ -74,12 +74,12 @@
* behaviuor in a subclass, and provide the latter to the
* QueuePort constructor.
*/
- QueuedSlavePort(const std::string& name, SimObject* owner,
+ QueuedResponsePort(const std::string& name, SimObject* owner,
RespPacketQueue &resp_queue, PortID id =
InvalidPortID) :
ResponsePort(name, owner, id), respQueue(resp_queue)
{ }
- virtual ~QueuedSlavePort() { }
+ virtual ~QueuedResponsePort() { }
/**
* Schedule the sending of a timing response.
@@ -97,13 +97,13 @@
};
/**
- * The QueuedMasterPort combines two queues, a request queue and a
+ * The QueuedRequestPort combines two queues, a request queue and a
* snoop response queue, that both share the same port. The flow
* control for requests and snoop responses are completely
* independent, and so each queue manages its own flow control
* (retries).
*/
-class QueuedMasterPort : public RequestPort
+class QueuedRequestPort : public RequestPort
{
protected:
@@ -127,7 +127,7 @@
* behaviuor in a subclass, and provide the latter to the
* QueuePort constructor.
*/
- QueuedMasterPort(const std::string& name, SimObject* owner,
+ QueuedRequestPort(const std::string& name, SimObject* owner,
ReqPacketQueue &req_queue,
SnoopRespPacketQueue &snoop_resp_queue,
PortID id = InvalidPortID) :
@@ -135,7 +135,7 @@
snoopRespQueue(snoop_resp_queue)
{ }
- virtual ~QueuedMasterPort() { }
+ virtual ~QueuedRequestPort() { }
/**
* Schedule the sending of a timing request.
diff --git a/src/mem/ruby/system/RubyPort.cc
b/src/mem/ruby/system/RubyPort.cc
index 4510e3a..43259eb 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -122,7 +122,7 @@
RubyPort::PioMasterPort::PioMasterPort(const std::string &_name,
RubyPort *_port)
- : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
+ : QueuedRequestPort(_name, _port, reqQueue, snoopRespQueue),
reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
{
DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name);
@@ -130,14 +130,14 @@
RubyPort::PioSlavePort::PioSlavePort(const std::string &_name,
RubyPort *_port)
- : QueuedSlavePort(_name, _port, queue), queue(*_port, *this)
+ : QueuedResponsePort(_name, _port, queue), queue(*_port, *this)
{
DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name);
}
RubyPort::MemMasterPort::MemMasterPort(const std::string &_name,
RubyPort *_port)
- : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
+ : QueuedRequestPort(_name, _port, reqQueue, snoopRespQueue),
reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
{
DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n",
_name);
@@ -146,7 +146,7 @@
RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort
*_port,
bool _access_backing_store, PortID id,
bool _no_retry_on_stall)
- : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this),
+ : QueuedResponsePort(_name, _port, queue, id), queue(*_port, *this),
access_backing_store(_access_backing_store),
no_retry_on_stall(_no_retry_on_stall)
{
diff --git a/src/mem/ruby/system/RubyPort.hh
b/src/mem/ruby/system/RubyPort.hh
index 1e21090..c764932 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -58,7 +58,7 @@
class RubyPort : public ClockedObject
{
public:
- class MemMasterPort : public QueuedMasterPort
+ class MemMasterPort : public QueuedRequestPort
{
private:
ReqPacketQueue reqQueue;
@@ -72,7 +72,7 @@
void recvRangeChange() {}
};
- class MemSlavePort : public QueuedSlavePort
+ class MemSlavePort : public QueuedResponsePort
{
private:
RespPacketQueue queue;
@@ -102,7 +102,7 @@
bool isPhysMemAddress(PacketPtr pkt) const;
};
- class PioMasterPort : public QueuedMasterPort
+ class PioMasterPort : public QueuedRequestPort
{
private:
ReqPacketQueue reqQueue;
@@ -116,7 +116,7 @@
void recvRangeChange();
};
- class PioSlavePort : public QueuedSlavePort
+ class PioSlavePort : public QueuedResponsePort
{
private:
RespPacketQueue queue;
diff --git a/src/mem/snoop_filter.hh b/src/mem/snoop_filter.hh
index 62d764e..668adfb 100644
--- a/src/mem/snoop_filter.hh
+++ b/src/mem/snoop_filter.hh
@@ -89,7 +89,7 @@
// Change for systems with more than 256 ports tracked by this object
static const int SNOOP_MASK_SIZE = 256;
- typedef std::vector<QueuedSlavePort*> SnoopList;
+ typedef std::vector<QueuedResponsePort*> SnoopList;
SnoopFilter (const SnoopFilterParams *p) :
SimObject(p), reqLookupResult(cachedLocations.end()),
diff --git a/src/mem/token_port.cc b/src/mem/token_port.cc
index 648d041..5a2462a 100644
--- a/src/mem/token_port.cc
+++ b/src/mem/token_port.cc
@@ -116,7 +116,7 @@
void
TokenSlavePort::recvRespRetry()
{
- // fallback to QueuedSlavePort-like impl for now
+ // fallback to QueuedResponsePort-like impl for now
panic_if(respQueue.empty(),
"Attempted to retry a response when no retry was queued!\n");
diff --git a/src/mem/tport.cc b/src/mem/tport.cc
index 2bcb022..8b8e937 100644
--- a/src/mem/tport.cc
+++ b/src/mem/tport.cc
@@ -43,7 +43,7 @@
SimpleTimingPort::SimpleTimingPort(const std::string& _name,
SimObject* _owner) :
- QueuedSlavePort(_name, _owner, queueImpl), queueImpl(*_owner, *this)
+ QueuedResponsePort(_name, _owner, queueImpl), queueImpl(*_owner, *this)
{
}
diff --git a/src/mem/tport.hh b/src/mem/tport.hh
index 6c560d3..0505fc1 100644
--- a/src/mem/tport.hh
+++ b/src/mem/tport.hh
@@ -56,7 +56,7 @@
* recvFunctional and recvTimingReq through recvAtomic. It is always a
* slave port.
*/
-class SimpleTimingPort : public QueuedSlavePort
+class SimpleTimingPort : public QueuedResponsePort
{
private:
@@ -64,7 +64,7 @@
/**
* The packet queue used to store outgoing responses. Note that
* the queue is made private and that we avoid overloading the
- * name used in the QueuedSlavePort. Access is provided through
+ * name used in the QueuedResponsePort. Access is provided through
* the queue reference in the base class.
*/
RespPacketQueue queueImpl;
diff --git a/src/mem/xbar.hh b/src/mem/xbar.hh
index 535277a..19fa097 100644
--- a/src/mem/xbar.hh
+++ b/src/mem/xbar.hh
@@ -373,7 +373,7 @@
bool gotAllAddrRanges;
/** The master and slave ports of the crossbar */
- std::vector<QueuedSlavePort*> slavePorts;
+ std::vector<QueuedResponsePort*> slavePorts;
std::vector<RequestPort*> masterPorts;
/** Port that handles requests that don't match any of the
interfaces.*/
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7d84d0df3d0003a3447c7118abcbba43443b3b23
Gerrit-Change-Number: 33494
Gerrit-PatchSet: 1
Gerrit-Owner: Eden Avivi <eav...@ucdavis.edu>
Gerrit-MessageType: newchange
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