Eden Avivi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33506 )
Change subject: misc: Master/Slave terminology
......................................................................
misc: Master/Slave terminology
Changed PioMasterPort and PioSlavePort
Change-Id: I8530e2271db14fe4b3f2bf0dfbc795e4fc2c135a
---
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/src/mem/ruby/system/RubyPort.cc
b/src/mem/ruby/system/RubyPort.cc
index 8c399b8..56c0d9b 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -76,7 +76,7 @@
// create the master ports based on the number of connected ports
for (size_t i = 0; i < p->port_master_connection_count; ++i) {
- master_ports.push_back(new PioMasterPort(csprintf("%s.master%d",
+ master_ports.push_back(new PioRequestPort(csprintf("%s.master%d",
name(), i), this));
}
}
@@ -121,7 +121,7 @@
return ClockedObject::getPort(if_name, idx);
}
-RubyPort::PioMasterPort::PioMasterPort(const std::string &_name,
+RubyPort::PioRequestPort::PioRequestPort(const std::string &_name,
RubyPort *_port)
: QueuedRequestPort(_name, _port, reqQueue, snoopRespQueue),
reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
@@ -129,7 +129,7 @@
DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name);
}
-RubyPort::PioSlavePort::PioSlavePort(const std::string &_name,
+RubyPort::PioResponsePort::PioResponsePort(const std::string &_name,
RubyPort *_port)
: QueuedResponsePort(_name, _port, queue), queue(*_port, *this)
{
@@ -156,7 +156,7 @@
}
bool
-RubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt)
+RubyPort::PioRequestPort::recvTimingResp(PacketPtr pkt)
{
RubyPort *rp = static_cast<RubyPort *>(&owner);
DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr());
@@ -192,7 +192,7 @@
}
bool
-RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt)
+RubyPort::PioResponsePort::recvTimingReq(PacketPtr pkt)
{
RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
@@ -213,7 +213,7 @@
}
Tick
-RubyPort::PioSlavePort::recvAtomic(PacketPtr pkt)
+RubyPort::PioResponsePort::recvAtomic(PacketPtr pkt)
{
RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
// Only atomic_noncaching mode supported!
@@ -584,7 +584,7 @@
}
AddrRangeList
-RubyPort::PioSlavePort::getAddrRanges() const
+RubyPort::PioResponsePort::getAddrRanges() const
{
// at the moment the assumption is that the master does not care
AddrRangeList ranges;
@@ -631,7 +631,7 @@
}
void
-RubyPort::PioMasterPort::recvRangeChange()
+RubyPort::PioRequestPort::recvRangeChange()
{
RubyPort &r = static_cast<RubyPort &>(owner);
r.gotAddrRanges--;
diff --git a/src/mem/ruby/system/RubyPort.hh
b/src/mem/ruby/system/RubyPort.hh
index 40f148c..9e87c0c 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -102,27 +102,27 @@
bool isPhysMemAddress(PacketPtr pkt) const;
};
- class PioMasterPort : public QueuedRequestPort
+ class PioRequestPort : public QueuedRequestPort
{
private:
ReqPacketQueue reqQueue;
SnoopRespPacketQueue snoopRespQueue;
public:
- PioMasterPort(const std::string &_name, RubyPort *_port);
+ PioRequestPort(const std::string &_name, RubyPort *_port);
protected:
bool recvTimingResp(PacketPtr pkt);
void recvRangeChange();
};
- class PioSlavePort : public QueuedResponsePort
+ class PioResponsePort : public QueuedResponsePort
{
private:
RespPacketQueue queue;
public:
- PioSlavePort(const std::string &_name, RubyPort *_port);
+ PioResponsePort(const std::string &_name, RubyPort *_port);
protected:
bool recvTimingReq(PacketPtr pkt);
@@ -205,15 +205,15 @@
retryList.push_back(port);
}
- PioMasterPort pioMasterPort;
- PioSlavePort pioSlavePort;
+ PioRequestPort pioMasterPort;
+ PioResponsePort pioSlavePort;
MemRequestPort memMasterPort;
MemResponsePort memSlavePort;
unsigned int gotAddrRanges;
/** Vector of M5 Ports attached to this Ruby port. */
typedef std::vector<MemResponsePort *>::iterator CpuPortIter;
- std::vector<PioMasterPort *> master_ports;
+ std::vector<PioRequestPort *> master_ports;
//
// Based on similar code in the M5 bus. Stores pointers to those ports
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8530e2271db14fe4b3f2bf0dfbc795e4fc2c135a
Gerrit-Change-Number: 33506
Gerrit-PatchSet: 1
Gerrit-Owner: Eden Avivi <eav...@ucdavis.edu>
Gerrit-MessageType: newchange
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