Eden Avivi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33505 )
Change subject: misc: Master/Slave terminology
......................................................................
misc: Master/Slave terminology
Changed MemMasterPort and MemSlavePort
Change-Id: I589906af48e44dc5a831350413d521a4dd7606f2
---
M src/mem/ruby/system/GPUCoalescer.cc
M src/mem/ruby/system/GPUCoalescer.hh
M src/mem/ruby/system/RubyPort.cc
M src/mem/ruby/system/RubyPort.hh
M src/mem/ruby/system/VIPERCoalescer.cc
5 files changed, 35 insertions(+), 33 deletions(-)
diff --git a/src/mem/ruby/system/GPUCoalescer.cc
b/src/mem/ruby/system/GPUCoalescer.cc
index 80bc19a..b2a6801 100644
--- a/src/mem/ruby/system/GPUCoalescer.cc
+++ b/src/mem/ruby/system/GPUCoalescer.cc
@@ -669,7 +669,7 @@
// back the requesting CU when we receive write
// complete callbacks for all issued Ruby requests of this
// instruction.
- RubyPort::MemSlavePort* mem_slave_port = ss->port;
+ RubyPort::MemResponsePort* mem_slave_port = ss->port;
GPUDynInstPtr gpuDynInst = nullptr;
@@ -783,7 +783,7 @@
for (auto& pkt : mylist) {
RubyPort::SenderState *ss =
safe_cast<RubyPort::SenderState *>(pkt->senderState);
- MemSlavePort *port = ss->port;
+ MemResponsePort *port = ss->port;
assert(port != NULL);
pkt->senderState = ss->predecessor;
diff --git a/src/mem/ruby/system/GPUCoalescer.hh
b/src/mem/ruby/system/GPUCoalescer.hh
index 0aee3ca..16323a7 100644
--- a/src/mem/ruby/system/GPUCoalescer.hh
+++ b/src/mem/ruby/system/GPUCoalescer.hh
@@ -135,7 +135,7 @@
{}
void
- addPendingReq(RubyPort::MemSlavePort* port, GPUDynInstPtr inst,
+ addPendingReq(RubyPort::MemResponsePort* port, GPUDynInstPtr inst,
bool usingRubyTester)
{
assert(port);
@@ -192,7 +192,7 @@
// which implies multiple ports per instruction. However, we need
// only 1 of the ports to call back the CU. Therefore, here we keep
// track the port that sent the first packet of this instruction.
- RubyPort::MemSlavePort* originalPort;
+ RubyPort::MemResponsePort* originalPort;
// similar to the originalPort, this gpuDynInstPtr is set only for
// the first packet of this instruction.
GPUDynInstPtr gpuDynInstPtr;
diff --git a/src/mem/ruby/system/RubyPort.cc
b/src/mem/ruby/system/RubyPort.cc
index 43259eb..8c399b8 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -68,7 +68,8 @@
// create the slave ports based on the number of connected ports
for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
- slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d",
name(),
+ slave_ports.push_back
+ (new MemResponsePort(csprintf("%s.slave%d", name(),
i), this, p->ruby_system->getAccessBackingStore(),
i, p->no_retry_on_stall));
}
@@ -135,7 +136,7 @@
DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name);
}
-RubyPort::MemMasterPort::MemMasterPort(const std::string &_name,
+RubyPort::MemRequestPort::MemRequestPort(const std::string &_name,
RubyPort *_port)
: QueuedRequestPort(_name, _port, reqQueue, snoopRespQueue),
reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
@@ -143,7 +144,8 @@
DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n",
_name);
}
-RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort
*_port,
+RubyPort::
+MemResponsePort::MemResponsePort(const std::string &_name, RubyPort *_port,
bool _access_backing_store, PortID id,
bool _no_retry_on_stall)
: QueuedResponsePort(_name, _port, queue, id), queue(*_port, *this),
@@ -165,7 +167,7 @@
return true;
}
-bool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt)
+bool RubyPort::MemRequestPort::recvTimingResp(PacketPtr pkt)
{
// got a response from a device
assert(pkt->isResponse());
@@ -173,7 +175,7 @@
// First we must retrieve the request port from the sender State
RubyPort::SenderState *senderState =
safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
- MemSlavePort *port = senderState->port;
+ MemResponsePort *port = senderState->port;
assert(port != NULL);
delete senderState;
@@ -231,7 +233,7 @@
}
bool
-RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt)
+RubyPort::MemResponsePort::recvTimingReq(PacketPtr pkt)
{
DPRINTF(RubyPort, "Timing request for address %#x on port %d\n",
pkt->getAddr(), id);
@@ -302,7 +304,7 @@
}
Tick
-RubyPort::MemSlavePort::recvAtomic(PacketPtr pkt)
+RubyPort::MemResponsePort::recvAtomic(PacketPtr pkt)
{
RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
// Only atomic_noncaching mode supported!
@@ -347,7 +349,7 @@
}
void
-RubyPort::MemSlavePort::addToRetryList()
+RubyPort::MemResponsePort::addToRetryList()
{
RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
@@ -362,7 +364,7 @@
}
void
-RubyPort::MemSlavePort::recvFunctional(PacketPtr pkt)
+RubyPort::MemResponsePort::recvFunctional(PacketPtr pkt)
{
DPRINTF(RubyPort, "Functional access for address: %#x\n",
pkt->getAddr());
@@ -437,7 +439,7 @@
// First we must retrieve the request port from the sender State
RubyPort::SenderState *senderState =
safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
- MemSlavePort *port = senderState->port;
+ MemResponsePort *port = senderState->port;
assert(port != NULL);
delete senderState;
@@ -450,8 +452,8 @@
RubyPort::trySendRetries()
{
//
- // If we had to stall the MemSlavePorts, wake them up because the
sequencer
- // likely has free resources now.
+ // If we had to stall the MemResponsePorts,
+ // wake them up because the sequencer likely has free resources now.
//
if (!retryList.empty()) {
// Record the current list of ports to retry on a temporary list
@@ -459,7 +461,7 @@
// an immediate retry, which may result in the ports being put
back on
// the list. Therefore we want to clear the retryList before
calling
// sendRetryReq.
- std::vector<MemSlavePort *> curRetryList(retryList);
+ std::vector<MemResponsePort *> curRetryList(retryList);
retryList.clear();
@@ -507,7 +509,7 @@
}
void
-RubyPort::MemSlavePort::hitCallback(PacketPtr pkt)
+RubyPort::MemResponsePort::hitCallback(PacketPtr pkt)
{
bool needsResponse = pkt->needsResponse();
@@ -598,7 +600,7 @@
}
bool
-RubyPort::MemSlavePort::isPhysMemAddress(PacketPtr pkt) const
+RubyPort::MemResponsePort::isPhysMemAddress(PacketPtr pkt) const
{
RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
return ruby_port->system->isMemAddr(pkt->getAddr())
diff --git a/src/mem/ruby/system/RubyPort.hh
b/src/mem/ruby/system/RubyPort.hh
index c764932..40f148c 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -58,21 +58,21 @@
class RubyPort : public ClockedObject
{
public:
- class MemMasterPort : public QueuedRequestPort
+ class MemRequestPort : public QueuedRequestPort
{
private:
ReqPacketQueue reqQueue;
SnoopRespPacketQueue snoopRespQueue;
public:
- MemMasterPort(const std::string &_name, RubyPort *_port);
+ MemRequestPort(const std::string &_name, RubyPort *_port);
protected:
bool recvTimingResp(PacketPtr pkt);
void recvRangeChange() {}
};
- class MemSlavePort : public QueuedResponsePort
+ class MemResponsePort : public QueuedResponsePort
{
private:
RespPacketQueue queue;
@@ -80,7 +80,7 @@
bool no_retry_on_stall;
public:
- MemSlavePort(const std::string &_name, RubyPort *_port,
+ MemResponsePort(const std::string &_name, RubyPort *_port,
bool _access_backing_store,
PortID id, bool _no_retry_on_stall);
void hitCallback(PacketPtr pkt);
@@ -137,8 +137,8 @@
struct SenderState : public Packet::SenderState
{
- MemSlavePort *port;
- SenderState(MemSlavePort * _port) : port(_port)
+ MemResponsePort *port;
+ SenderState(MemResponsePort * _port) : port(_port)
{}
};
@@ -191,15 +191,15 @@
bool m_usingRubyTester;
System* system;
- std::vector<MemSlavePort *> slave_ports;
+ std::vector<MemResponsePort *> slave_ports;
private:
- bool onRetryList(MemSlavePort * port)
+ bool onRetryList(MemResponsePort * port)
{
return (std::find(retryList.begin(), retryList.end(), port) !=
retryList.end());
}
- void addToRetryList(MemSlavePort * port)
+ void addToRetryList(MemResponsePort * port)
{
if (onRetryList(port)) return;
retryList.push_back(port);
@@ -207,19 +207,19 @@
PioMasterPort pioMasterPort;
PioSlavePort pioSlavePort;
- MemMasterPort memMasterPort;
- MemSlavePort memSlavePort;
+ MemRequestPort memMasterPort;
+ MemResponsePort memSlavePort;
unsigned int gotAddrRanges;
/** Vector of M5 Ports attached to this Ruby port. */
- typedef std::vector<MemSlavePort *>::iterator CpuPortIter;
+ typedef std::vector<MemResponsePort *>::iterator CpuPortIter;
std::vector<PioMasterPort *> master_ports;
//
// Based on similar code in the M5 bus. Stores pointers to those ports
// that should be called when the Sequencer becomes available after a
stall.
//
- std::vector<MemSlavePort *> retryList;
+ std::vector<MemResponsePort *> retryList;
bool m_isCPUSequencer;
};
diff --git a/src/mem/ruby/system/VIPERCoalescer.cc
b/src/mem/ruby/system/VIPERCoalescer.cc
index eafce6d..a8a3aa9 100644
--- a/src/mem/ruby/system/VIPERCoalescer.cc
+++ b/src/mem/ruby/system/VIPERCoalescer.cc
@@ -248,7 +248,7 @@
RubyPort::SenderState *ss =
safe_cast<RubyPort::SenderState *>
(writeCompletePkt->senderState);
- MemSlavePort *port = ss->port;
+ MemResponsePort *port = ss->port;
assert(port != NULL);
writeCompletePkt->senderState = ss->predecessor;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I589906af48e44dc5a831350413d521a4dd7606f2
Gerrit-Change-Number: 33505
Gerrit-PatchSet: 1
Gerrit-Owner: Eden Avivi <[email protected]>
Gerrit-MessageType: newchange
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