Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/37616 )
Change subject: arch-arm: VSTCR_EL2/VSTTBR_EL2 accessible in secure mode
only
......................................................................
arch-arm: VSTCR_EL2/VSTTBR_EL2 accessible in secure mode only
We should trigger an Undefined Instruction if those registers
are accessed in non-secure mode
Change-Id: I45ec01e9e4ae9a38d59e56a51e198b4199a7d814
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Ciro Santilli <[email protected]>
Reviewed-by: Nikos Nikoleris <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37616
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/miscregs.cc
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
Ciro Santilli: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 8110a19..825811f 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -4907,9 +4907,9 @@
.hyp().mon()
.mapsTo(MISCREG_VTCR);
InitReg(MISCREG_VSTTBR_EL2)
- .hyp().mon();
+ .hypSecure().mon();
InitReg(MISCREG_VSTCR_EL2)
- .hyp().mon();
+ .hypSecure().mon();
InitReg(MISCREG_TTBR0_EL3)
.mon();
InitReg(MISCREG_TCR_EL3)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I45ec01e9e4ae9a38d59e56a51e198b4199a7d814
Gerrit-Change-Number: 37616
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Ciro Santilli <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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