> One completely different solution would be to do what you're saying > and just not have the timing simple CPU work like it does. I think > it's organized a lot like the atomic simple CPU because it used to be > a part of it, but really a more natural organization would be as a > state machine where activity was broken by hard lines into states. > There might be a little more overhead that way, but it would make it > much easier for non-experts to see what the heck is going on in there. > It would also help the experts avoid introducing bugs because there > are so many interactions to consider.
This seems pretty reasonable to me. There are already states in the models to deal with cache misses and such, so adding another state for the different phases of a memory access seems reasonable. The impact probably wouldn't be huge given the fact that the cache is probably pretty expensive compared to the CPU when executing memory ops. Nate _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
