I have been trying to trace the output of the m5term to see what gives rise to the error. I have been able to go from the beginning to the "jumping to kernel " part of the output which gets printed from console.c in alpha_systems.
But I am not able to track the next step from there, which code is responsible for the next set of outputs. Could someone help in this regard? Thanks Pritha On Mon, Jul 5, 2010 at 12:10 AM, Pritha Ghoshal <pritha9...@tamu.edu> wrote: > I am not sure, I am trying to check how much is working in full system > mode. Has ruby been used only in system emulation mode till now? > > Pritha > > > On Sun, Jul 4, 2010 at 2:27 AM, nathan binkert <n...@binkert.org> wrote: > >> Is Ruby supposed to work in FS mode right now? >> >> Nate >> >> > Just to clarify, the –caches and –l2cache flags are not used by Ruby. >> Also >> > you might want to specify the –num-dirs=4 to create a symmetric system, >> but >> > if you don’t, I believe the default of 1 directory should still work. >> > >> > There are a couple things I would like you to try: >> > >> > 1. Could you compile the m5.debug version of MOESI_hammer and see >> if >> > you can gather any additional information. >> > >> > 2. Could you run with the classic memory system using fs.py and >> timing >> > mode and see if you encounter problems. >> > >> > Thanks, >> > >> > Brad >> > >> > >> > >> > From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] On >> Behalf >> > Of Pritha Ghoshal >> > Sent: Friday, July 02, 2010 11:13 AM >> > To: M5 Developer List >> > Subject: Re: [m5-dev] MESI_CMP directory protocol with more than 2 >> > processors >> > >> > >> > >> > Hi Brad, >> > >> > I tried MOESI Hammer protocol with 4 processors. I am still getting an >> > error: >> > SMP: Processor 1 failed to start. >> > Slave CPU 2 console command START >> > SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb >> FFFFFFFE00000000 >> > my_rpb FFFFFC0000018680 my_rpb_phys 18680 >> > SMP: Processor 3 failed to start. >> > Brought up 2 CPUs >> > >> > My command line is >> > ./build/ALPHA_FS_MOESI_hammer/m5.opt ./configs/example/ruby_fs.py -t >> > --caches --l2cache -n 4 -b bodytrack >> > >> > Thanks for your help.. >> > >> > Pritha >> > >> > On Fri, Jul 2, 2010 at 11:04 AM, Beckmann, Brad <brad.beckm...@amd.com> >> > wrote: >> > >> > Hi Pritha, >> > >> > In general, the protocols in M5 aren’t quite ready for “primetime” and I >> > wouldn’t be surprised if you encounter bugs like the one you mentioned. >> I’m >> > happy to help you out and determine what the problem may be. However, >> be >> > warned that I might not be able to immediately create and push in a fix. >> > >> > Could you send me the specific command line you ran? Also could you >> confirm >> > that the MOESI hammer protocol with 4 processors works and that your >> problem >> > is isolated to the MESI CMP directory protocol. >> > >> > Thanks, >> > >> > Brad >> > >> > >> > >> > From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] On >> Behalf >> > Of Pritha Ghoshal >> > Sent: Thursday, July 01, 2010 7:25 PM >> > To: m5-dev@m5sim.org >> > Subject: [m5-dev] MESI_CMP directory protocol with more than 2 >> processors >> > >> > >> > >> > Hi, >> > >> > I am trying to run MESI CMP directory protocol on M5. It seems to be >> > functioning properly with 1 processor and 2 processors. But when I tried >> to >> > run 4 processors, am getting the error: >> > >> > SMP: Processor 1 failed to start. >> > >> > SMP: Processor 2 failed to start. >> > >> > Therefore only 2 processors are getting launched, and even after that >> its >> > not executing properly, am getting the following error repeatedly after >> > sometime >> > >> > hda: dma_timer_expiry: dma status == 0x64 >> > >> > hda: DMA interrupt recovery >> > >> > hda: lost interrupt >> > >> > Could someone help me regarding this? I am not sure where to look into >> for >> > trying to understand the reason of the problem... >> > >> > Thank you >> > Pritha >> > >> > _______________________________________________ >> > m5-dev mailing list >> > m5-dev@m5sim.org >> > http://m5sim.org/mailman/listinfo/m5-dev >> > >> > >> > >> > _______________________________________________ >> > m5-dev mailing list >> > m5-dev@m5sim.org >> > http://m5sim.org/mailman/listinfo/m5-dev >> > >> > >> _______________________________________________ >> m5-dev mailing list >> m5-dev@m5sim.org >> http://m5sim.org/mailman/listinfo/m5-dev >> > >
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