Hi Min,
The way that the TLB deals with a timing translation is specific to each
ISA. I don't have much experience with anything other than Power but
for that ISA, yes, you're correct. The timing translation is just a
wrapper around the atomic translation. It seems from a quick check that
Alpha is the same.
If you actually wanted to have the fetch translation finish on a
different cycle to the one it was initiated on then you would have to
make some changes to the fetch stage to allow that. I wouldn't have
thought it would be too difficult but might require splitting up several
functions into code that's executed before the translation and code
that's executed afterwards.
Cheers
Tim
On 12/07/2010 18:14, Min Kyu Jeong wrote:
Hi,
This question is regarding the changeset
(http://repo.m5sim.org/m5?cmd=changeset;node=a123bd350935).
This initiates a timing translation and passes the read or write on
to the
processor before waiting for it to finish
It looks like even in the event of TLB miss, TLB-walk does not delay the
actual execution of the loads. Am I correct?
I was trying to find a reference for replacing the translateAtomic() in
the fetch stage w/ translateTIming(). It would require some mechanism to
stop the actual fetch until the translation is finished - which doesn't
seem to exist in the O3 CPU even for the data translation.
Thanks,
Min
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Timothy M. Jones
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