Hi, This question is regarding the changeset ( http://repo.m5sim.org/m5?cmd=changeset;node=a123bd350935).
This initiates a timing translation and passes the read or write on to the processor before waiting for it to finish It looks like even in the event of TLB miss, TLB-walk does not delay the actual execution of the loads. Am I correct? I was trying to find a reference for replacing the translateAtomic() in the fetch stage w/ translateTIming(). It would require some mechanism to stop the actual fetch until the translation is finished - which doesn't seem to exist in the O3 CPU even for the data translation. Thanks, Min
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