I think this is the first time I've updated an existing diff via reviewboard, and I thought it would give me a chance to enter some comments on the website before publishing it like a new diff, but it didn't. so here are the comments that go with this diff:
I had originally been more aggressive about common prefix extraction, but there were some glitches that made me go with the path-based approach... however, in the process of uploading this diff I thought of some fixes. So consider this second diff as an alternative and not necessarily a replacement. Example output for the new diff, corresponding to the previous example selection: [ CXX] ALPHA_SE/sim/main: .cc -> .do Defining FAST_ALLOC_DEBUG as 0 in build/ALPHA_SE/config/fast_alloc_debug.hh. Defining FAST_ALLOC_STATS as 0 in build/ALPHA_SE/config/fast_alloc_stats.hh. Defining NO_FAST_ALLOC as 0 in build/ALPHA_SE/config/no_fast_alloc.hh. [ TRACING] -> ALPHA_SE/base/traceflags.hh [ CXX] ALPHA_SE/python/swig/pyevent: .cc -> .do Defining FULL_SYSTEM as 0 in build/ALPHA_SE/config/full_system.hh. [SO PARAM] MemObject -> ALPHA_SE/params/MemObject.hh [SO PARAM] SimObject -> ALPHA_SE/params/SimObject.hh [GENERATE] -> ALPHA_SE/arch/isa_traits.hh [ CXX] ALPHA_SE/python/swig/pyobject: .cc -> .do [ SWIG] ALPHA_SE/python/swig/core: .i -> _wrap.cc, .py [ CXX] ALPHA_SE/python/swig/core_wrap: .cc -> .do [ SWIG] ALPHA_SE/python/swig/debug: .i -> _wrap.cc, .py [ CXX] ALPHA_SE/python/swig/debug_wrap: .cc -> .do ... [GENERATE] -> ALPHA_SE/arch/vtophys.hh [ CFG ISA] alpha, arm, mips, no, power, sparc, x86 -> ALPHA_SE/config/the_isa.hh [GENERATE] -> ALPHA_SE/arch/types.hh [GENERATE] -> ALPHA_SE/arch/registers.hh [GENERATE] static_inst_exec_sigs.hh: AtomicSimpleCPU, InOrderCPU, O3CPU, TimingSimpleCPU [EN PARAM] MemoryMode -> ALPHA_SE/enums/MemoryMode.hh [SO PARAM] System -> ALPHA_SE/params/System.hh [EN PARAM] OpClass -> ALPHA_SE/enums/OpClass.hh [SO PARAM] PhysicalMemory -> ALPHA_SE/params/PhysicalMemory.hh [ISA DESC] ALPHA_SE/arch/alpha/: isa/main.isa -> decoder.cc, decoder.hh, max_inst_regs.hh, atomic_simple_cpu_exec.cc, inorder_cpu_exec.cc, o3_cpu_exec.cc, timing_simple_cpu_exec.cc [ CXX] ALPHA_SE/base/remote_gdb: .cc -> .do [ CXX] ALPHA_SE/base/socket: .cc -> .do ... [SW PARAM] Process -> ALPHA_SE/python/m5/internal/vptype_Process.i [BLDPARAM] Process -> ALPHA_SE/python/m5/internal/param_Process.i [BLDPARAM] SimObject -> ALPHA_SE/python/m5/internal/param_SimObject.i [BLDPARAM] System -> ALPHA_SE/python/m5/internal/param_System.i [ENUMSWIG] MemoryMode -> ALPHA_SE/python/m5/internal/enum_MemoryMode.i [BLDPARAM] PhysicalMemory -> ALPHA_SE/python/m5/internal/param_PhysicalMemory.i [BLDPARAM] MemObject -> ALPHA_SE/python/m5/internal/param_MemObject.i [ SWIG] ALPHA_SE/python/m5/internal/vptype_Process: .i -> _wrap.cc, .py [ CXX] ALPHA_SE/python/m5/internal/vptype_Process_wrap: .cc -> .do [SW PARAM] AddrRange -> ALPHA_SE/python/m5/internal/vptype_AddrRange.i [ SWIG] ALPHA_SE/python/m5/internal/vptype_AddrRange: .i -> _wrap.cc, .py [ CXX] ALPHA_SE/python/m5/internal/vptype_AddrRange_wrap: .cc -> .do ... [EMBED PY] ALPHA_SE/python/m5/internal/param_BaseSimpleCPU.py: -> .cc [ CXX] ALPHA_SE/python/m5/internal/param_BaseSimpleCPU.py: .cc -> .do [EMBED PY] ALPHA_SE/python/m5/internal/param_LiveProcess.py: -> .cc [ CXX] ALPHA_SE/python/m5/internal/param_LiveProcess.py: .cc -> .do [ TRACING] -> ALPHA_SE/base/traceflags.py [EMBED PY] ALPHA_SE/base/traceflags.py: -> .cc [ CXX] ALPHA_SE/base/traceflags.py: .cc -> .do [ CXX] ALPHA_SE/base/date: .cc -> .do [ LINK] -> ALPHA_SE/m5.debug
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