I don't recall all the details about what got me going on this, but I think a couple of the specific things I didn't like were (1) if you compile multiple binaries at the same time (e.g., m5.debug and m5.opt) the CXX lines print the source file which doesn't give you enough information to know which one is compiling and (2) for swig, it prints the foo_wrap.cc target file name, which takes some (admittedly little) inside knowledge to map back to the foo.i file if you care, and doesn't mention the generated .py file.
Anyway, it was just enough annoyance to lead me to think that the problem was inconsistently printing the source sometimes and the target other times... one simple solution would be just to consistently print one or the other, but since it's not obvious which one is more useful, I thought why not print both. And here I am. I think this version would be helpful in addressing the newbies-don't-know-where-generated-files-come-from problem too, if they just bother to look at the output while it builds. What don't you like about these newer versions? Just that they're more verbose? Steve On Mon, Jan 3, 2011 at 3:45 PM, Gabe Black <gbl...@eecs.umich.edu> wrote: > I like the original (Ali's version) better. When was it confusing? > Perhaps there's a particular action that would be better the other way > around. Maybe we should have graduated levels of verbosity for this > stuff where, for example, 0 is Ali's version, 1 is this version, and 2 > is the full command. > > Gabe > > Steve Reinhardt wrote: > > This is an automatically generated e-mail. To reply, visit: > > http://reviews.m5sim.org/r/366/ > > > > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, > > and Nathan Binkert. > > By Steve Reinhardt. > > > > > > Description > > > > scons: show sources and targets when building. > > > > I like the brevity of Ali's recent change, but the ambiguity of > > sometimes showing the source and sometimes the target is a little > > confusing. This patch makes scons typically list all sources and > > all targets for each action, with the common path prefix factored > > out for brevity. It's a little more verbose now but also more > > informative. > > > > I'm not intending to add this to the commit message, but for review > purposes, here's some example output: > > [ CXX] ALPHA_SE/sim: main.cc -> main.do > > Defining FAST_ALLOC_DEBUG as 0 in > build/ALPHA_SE/config/fast_alloc_debug.hh. > > Defining FAST_ALLOC_STATS as 0 in > build/ALPHA_SE/config/fast_alloc_stats.hh. > > Defining NO_FAST_ALLOC as 0 in build/ALPHA_SE/config/no_fast_alloc.hh. > > [ TRACING] ALPHA_SE/base: -> traceflags.hh > > [ CXX] ALPHA_SE/python/swig: pyevent.cc -> pyevent.do > > Defining FULL_SYSTEM as 0 in build/ALPHA_SE/config/full_system.hh. > > [SO PARAM] MemObject -> ALPHA_SE/params/MemObject.hh > > [SO PARAM] SimObject -> ALPHA_SE/params/SimObject.hh > > [GENERATE] ALPHA_SE/arch: -> isa_traits.hh > > [ CXX] ALPHA_SE/python/swig: pyobject.cc -> pyobject.do > > [ SWIG] ALPHA_SE/python/swig: core.i -> core_wrap.cc, core.py > > [ CXX] ALPHA_SE/python/swig: core_wrap.cc -> core_wrap.do > > [ SWIG] ALPHA_SE/python/swig: debug.i -> debug_wrap.cc, debug.py > > [ CXX] ALPHA_SE/python/swig: debug_wrap.cc -> debug_wrap.do > > (...skipping...) > > [GENERATE] ALPHA_SE/arch: -> vtophys.hh > > [ CFG ISA] alpha, arm, mips, no, power, sparc, x86 -> > ALPHA_SE/config/the_isa.hh > > [GENERATE] ALPHA_SE/arch: -> types.hh > > [GENERATE] ALPHA_SE/arch: -> registers.hh > > [GENERATE] static_inst_exec_sigs.hh: AtomicSimpleCPU, InOrderCPU, O3CPU, > TimingSimpleCPU > > [EN PARAM] MemoryMode -> ALPHA_SE/enums/MemoryMode.hh > > [SO PARAM] System -> ALPHA_SE/params/System.hh > > [EN PARAM] OpClass -> ALPHA_SE/enums/OpClass.hh > > [SO PARAM] PhysicalMemory -> ALPHA_SE/params/PhysicalMemory.hh > > [ISA DESC] ALPHA_SE/arch/alpha: isa/main.isa -> decoder.cc, decoder.hh, > max_inst_regs.hh, atomic_simple_cpu_exec.cc, inorder_cpu_exec.cc, > o3_cpu_exec.cc, timing_simple_cpu_exec.cc > > [ CXX] ALPHA_SE/base: remote_gdb.cc -> remote_gdb.do > > [ CXX] ALPHA_SE/base: socket.cc -> socket.do > > (...skipping...) > > [SW PARAM] Process -> ALPHA_SE/python/m5/internal/vptype_Process.i > > [BLDPARAM] Process -> ALPHA_SE/python/m5/internal/param_Process.i > > [BLDPARAM] SimObject -> ALPHA_SE/python/m5/internal/param_SimObject.i > > [BLDPARAM] System -> ALPHA_SE/python/m5/internal/param_System.i > > [ENUMSWIG] MemoryMode -> ALPHA_SE/python/m5/internal/enum_MemoryMode.i > > [BLDPARAM] PhysicalMemory -> > ALPHA_SE/python/m5/internal/param_PhysicalMemory.i > > [BLDPARAM] MemObject -> ALPHA_SE/python/m5/internal/param_MemObject.i > > [ SWIG] ALPHA_SE/python/m5/internal: vptype_Process.i -> > vptype_Process_wrap.cc, vptype_Process.py > > [ CXX] ALPHA_SE/python/m5/internal: vptype_Process_wrap.cc -> > vptype_Process_wrap.do > > [SW PARAM] AddrRange -> ALPHA_SE/python/m5/internal/vptype_AddrRange.i > > [ SWIG] ALPHA_SE/python/m5/internal: vptype_AddrRange.i -> > vptype_AddrRange_wrap.cc, vptype_AddrRange.py > > [ CXX] ALPHA_SE/python/m5/internal: vptype_AddrRange_wrap.cc -> > vptype_AddrRange_wrap.do > > (...skipping...) > > [EMBED PY] ALPHA_SE/python/m5/internal: param_BaseSimpleCPU.py -> > param_BaseSimpleCPU.py.cc > > [ CXX] ALPHA_SE/python/m5/internal: param_BaseSimpleCPU.py.cc -> > param_BaseSimpleCPU.py.do > > [EMBED PY] ALPHA_SE/python/m5/internal: param_LiveProcess.py -> > param_LiveProcess.py.cc > > [ CXX] ALPHA_SE/python/m5/internal: param_LiveProcess.py.cc -> > param_LiveProcess.py.do > > [ TRACING] ALPHA_SE/base: -> traceflags.py > > [EMBED PY] ALPHA_SE/base: traceflags.py -> traceflags.py.cc > > [ CXX] ALPHA_SE/base: traceflags.py.cc -> traceflags.py.do > > [ CXX] ALPHA_SE/base: date.cc -> date.do > > [ LINK] ALPHA_SE: -> m5.debug > > > > > > > > Testing > > > > quick regressions pass > > > > > > Diffs > > > > * SConstruct (7338bc628489) > > * src/SConscript (7338bc628489) > > * src/arch/SConscript (7338bc628489) > > * src/arch/isa_parser.py (7338bc628489) > > > > View Diff <http://reviews.m5sim.org/r/366/diff/> > > > > ------------------------------------------------------------------------ > > > > _______________________________________________ > > m5-dev mailing list > > m5-dev@m5sim.org > > http://m5sim.org/mailman/listinfo/m5-dev > > > > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev >
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