I forgot that the memtester includes functional accesses. That is a good suggestion, especially when it comes to testing the situations where Ruby can't satisfy the functional access due to contention with timing accesses.
The memtester does run with Ruby (it actually runs every night in the regression tester), however the percentage of functional accesses is currently set to zero. See configs/example/ruby_mem_test.py. You'll obviously want to change that and include code within src/cpu/testers/memtest/* to handle failed functional accesses. If you don't want to initially deal with the failure situations, you can set the functional access percentage to 100% and that should always work. Brad > -----Original Message----- > From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] > On Behalf Of Steve Reinhardt > Sent: Tuesday, March 01, 2011 10:49 AM > To: M5 Developer List > Subject: Re: [m5-dev] Testing Functional Access > > The m5 memtester supports functional accesses (there's a > percent_functional parameter on the MemTest object). I don't know if > anyone's run the memtester with Ruby though. Seems like it should work. > > Steve > > On Tue, Mar 1, 2011 at 8:39 AM, Joel Hestness > <hestn...@cs.utexas.edu>wrote: > > > Hi Nilay, > > I don't know if there is a regression for it, but the M5 utility > > (./util/m5/) sets up functional accesses to memory. For instance, in > > FS, if you specify an rcS script to fs.py and call % /sbin/m5 > > readfile from the command line of the simulated system, it will read > > the specified rcS file off the host machine's disk and send it to the > > memory of the simulated system using functional accesses. I think > > there are other functional access examples in the magic that the M5 > > utility provides. > > Hope this helps, > > Joel > > > > > > > > On Tue, Mar 1, 2011 at 8:51 AM, Nilay <ni...@cs.wisc.edu> wrote: > > > > > How can I test whether or not functional accesses to the memory are > > > working correctly? Do we have some regression test for this? > > > > > > Thanks > > > Nilay > > > > > > _______________________________________________ > > > m5-dev mailing list > > > m5-dev@m5sim.org > > > http://m5sim.org/mailman/listinfo/m5-dev > > > > > > > > > > > -- > > Joel Hestness > > PhD Student, Computer Architecture > > Dept. of Computer Science, University of Texas - Austin > > http://www.cs.utexas.edu/~hestness > > _______________________________________________ > > m5-dev mailing list > > m5-dev@m5sim.org > > http://m5sim.org/mailman/listinfo/m5-dev > > > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
