I believe the L1DcacheMemory is created right after system because inside each protocol file the first thing attached to the system is the l1 controllers. That way the controllers get a more descriptive name than what they are as related to the topology.
I'm still a little confused by the cycle error. If the parent.any call searches the graph for the close object of that particular type, wouldn't you always get a cycle using parent.any? Or are other uses of parent.any more of an uncle search than a true parent search? Brad > -----Original Message----- > From: m5-dev-boun...@m5sim.org [mailto:m5-dev-boun...@m5sim.org] > On Behalf Of Steve Reinhardt > Sent: Wednesday, March 09, 2011 5:22 PM > To: M5 Developer List > Subject: Re: [m5-dev] Functional Interface in Ruby > > It seems odd that it tries to create L1DcacheMemory right after it creates > system. Can you add print statements like in this patch and see what it > shows? > > diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py > --- a/src/python/m5/SimObject.py > +++ b/src/python/m5/SimObject.py > @@ -843,8 +843,11 @@ > > # Call C++ to create C++ object corresponding to this object > def createCCObject(self): > + print "Creating", self, "params" > self.getCCParams() > + print "Creating", self > self.getCCObject() # force creation > + print "Done creating", self > > def getValue(self): > return self.getCCObject() > > > On Wed, Mar 9, 2011 at 2:34 PM, Nilay Vaish <ni...@cs.wisc.edu> wrote: > > > Creating root > > Creating system.physmem > > Creating system > > Creating system.l1_cntrl0.L1DcacheMemory Creating system.ruby Creating > > system.ruby.network Creating system.ruby.network.topology Creating > > system.ruby.network.topology.ext_links0 > > Creating system.l1_cntrl0 > > Creating system.l1_cntrl0.L1DcacheMemory > > > > This is the output I obtained from SimObject.py, clearly there is a cycle. > > Should not the cache controllers be part of ruby, instead of being > > part of system? Once they become part of ruby, it should be possible > > to traverse the controller array and figure out all the caches. > > > > > > Nilay > > > > On Wed, 9 Mar 2011, Steve Reinhardt wrote: > > > > I think you're looking in the wrong place... you want to look at > >> getCCObject() in src/python/m5/SimObject.py where the error message > >> is coming from, and see if you can add some print statements there. > >> > >> Steve > >> > >> On Wed, Mar 9, 2011 at 11:27 AM, Nilay Vaish <ni...@cs.wisc.edu> wrote: > >> > >> What exactly happens on the function call > >> Param.RubySystem(Parent.any, > >>> "Ruby System") ? > >>> > >>> Nilay > >>> > >>> > >>> On Wed, 9 Mar 2011, Steve Reinhardt wrote: > >>> > >>> Does the RubySystem object have a pointer to a RubyCache object? > >>> > >>>> > >>>> You could also go into the python code and add some print > >>>> statements to get a clue about where the cycle is occurring. > >>>> > >>>> Steve > >>>> > >>>> On Wed, Mar 9, 2011 at 4:51 AM, Nilay <ni...@cs.wisc.edu> wrote: > >>>> > >>>> Brad, given current versions of MESI_CMP_directory.py and Ruby.py, > >>>> the > >>>> > >>>>> following change to the way cache memory is added to the system > >>>>> creates a loop. What am I missing here? > >>>>> > >>>>> class RubyAbstractMemory(SimObject): > >>>>> type = 'RubyAbstractMemory' > >>>>> cxx_class = 'AbstractMemory' > >>>>> system = Param.RubySystem(Parent.any,"Ruby System"); > >>>>> > >>>>> class RubyCache(RubyAbstractMemory): > >>>>> type = 'RubyCache' > >>>>> cxx_class = 'CacheMemory' > >>>>> size = Param.MemorySize("capacity in bytes"); latency = > >>>>> Param.Int(""); assoc = Param.Int(""); replacement_policy = > >>>>> Param.String("PSEUDO_LRU", ""); start_index_bit = Param.Int(6, > >>>>> "index start, default 6 for 64-byte line"); > >>>>> > >>>>> -- > >>>>> Nilay > >>>>> > >>>>> _______________________________________________ > >>>>> > >>>> _______________________________________________ > > m5-dev mailing list > > m5-dev@m5sim.org > > http://m5sim.org/mailman/listinfo/m5-dev > > > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
