Hi all I tried to print the list of source registers in a given assembly instruction during the decode stage for ARM ISA. It turns out that many instructions have Register 33 as one of the source registers. I would like to know what this Register 33 signifies.
Also I would like to know on what basis a macroop is split into microops since they introduce a lot of temporary registers. Is there a way to disable predication in ARM ISA while compiling? Thanks V Vanchinathan
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