In general control registers are not often renamed (regardless of ISA - ARM, x86, etc). If any instruction modifies the CPSR, it should be marked as "serializing". This ensures that any writes to the register will be properly seen by any younger instructions. It works by not letting any younger instructions enter the processor back-end until the CPSR write completes. These control registers tend to be mostly read-only, so tolerating a pipeline stall on writes is not unreasonable.
So, it likely is being used, it's just not renamed. On Fri, Jan 3, 2014 at 1:41 AM, Vanchinathan Venkataramani < dcsv...@gmail.com> wrote: > Thanks a lot for your reply. > > Similar to R33, R37-R39 and so on there is register with id 1416 which > exists as a source for many instructions. I found that this instruction is > the CPSR register. > > I tried looking at the rename and iew stages for a given instruction. It > turns out that this register is being accessed in rename stage but not in > iew stage. Does this mean that the CPSR is not required for these > instructions? > > Thanks > V Vanchinathan > > > On Thu, Jan 2, 2014 at 10:03 PM, Mitch Hayenga < > mitch.hayenga+g...@gmail.com> wrote: > >> R33 is a "zero register". It is used whenever a zero is required. It is >> also often sourced unnecessarily if an instruction requires fewer source >> registers. >> >> In gem5 the basis for splitting is solely up to whoever wrote the ISA >> decoder. For arm its mostly what you would expect 2 real sources (not >> counting flags that can add more. R37-39 or so are the flags). >> >> In the past I tried to find a way to compile without predication too. >> Never found a way. >> >> Hope this helps. >> >> Sent from my phone. >> On Jan 2, 2014 7:38 AM, "Vanchinathan Venkataramani" <dcsv...@gmail.com> >> wrote: >> >>> Hi all >>> >>> I tried to print the list of source registers in a given assembly >>> instruction during the decode stage for ARM ISA. It turns out that many >>> instructions have Register 33 as one of the source registers. I would like >>> to know what this Register 33 signifies. >>> >>> Also I would like to know on what basis a macroop is split into microops >>> since they introduce a lot of temporary registers. >>> >>> Is there a way to disable predication in ARM ISA while compiling? >>> >>> Thanks >>> V Vanchinathan >>> >>> _______________________________________________ >>> gem5-users mailing list >>> gem5-users@gem5.org >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>> >> >> _______________________________________________ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> > > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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