R33 is a "zero register". It is used whenever a zero is required. It is also often sourced unnecessarily if an instruction requires fewer source registers.
In gem5 the basis for splitting is solely up to whoever wrote the ISA decoder. For arm its mostly what you would expect 2 real sources (not counting flags that can add more. R37-39 or so are the flags). In the past I tried to find a way to compile without predication too. Never found a way. Hope this helps. Sent from my phone. On Jan 2, 2014 7:38 AM, "Vanchinathan Venkataramani" <dcsv...@gmail.com> wrote: > Hi all > > I tried to print the list of source registers in a given assembly > instruction during the decode stage for ARM ISA. It turns out that many > instructions have Register 33 as one of the source registers. I would like > to know what this Register 33 signifies. > > Also I would like to know on what basis a macroop is split into microops > since they introduce a lot of temporary registers. > > Is there a way to disable predication in ARM ISA while compiling? > > Thanks > V Vanchinathan > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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