Checkpointing is supported in O3CPU for all ISAs (well at least x86 and
ARM so I'm going to say Alpha too since they share most of the code in
src/cpu/o3 anyway) to handle branch mispredictions/load-store dependency
mispredictions (or anything that squashes the pipeline, really).
It is not done by having explicit checkpoints as if I remember
correctly, each new mapping attributed at rename carries the previous
mapping, so you can rollback by restoring older mappings one by one.
I believe runahead is not supported in gem5 at all, you would need to
add it and merge it with the existing checkpointing scheme.
Or maybe you meant speculative execution, in which case, yes, and it's
all in src/cpu/o3/rename_impl.hh and src/cpu/o3/rename.hh.
Le 11/04/2015 23:06, Murat Koksal a écrit :
Hello,
Is the Alpha architecture implemented in gem5 (for o3cpu and inorder)
a checkpointing architecture, i.e. is checkpointing used to save
register file state to support runahead execution?
Thanks.
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Arthur Perais
INRIA Bretagne Atlantique
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