I am trying to connect the L1D to the CPU dcache port over an XBar (I intend to connect another memory to this XBar), however, when making this connection, I observe that the bandwidth to my L1 halves due to XBar contention, however, I am modelling this as a 0-latency XBar with effectively infinite width. Does anyone have any idea what I could be doing wrong? _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] XBar on dcache port impacting BW?
fisher.xue--- via gem5-users Tue, 13 Oct 2020 10:52:14 -0700
- [gem5-users] XBar on dcache port impacting BW... fisher.xue--- via gem5-users
- [gem5-users] Re: XBar on dcache port imp... Mahyar Samani via gem5-users
- [gem5-users] Re: XBar on dcache port... Xue, Fisher via gem5-users
- [gem5-users] Re: XBar on dcache ... Mahyar Samani via gem5-users
- [gem5-users] Re: XBar on dca... Xue, Fisher via gem5-users