Hey Mahyar,
Thanks for the response! I’m actually not seeing the 1 packet per cycle
expectation…
I think I have root-caused the issue to the timing calculation in the XBar,
however, I’m not sure if this is an intentional design choice or something else:
It calculates the time for a packet as
packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
however, I think this will require any packet of size to spend 2 cycles in the
XBar, limiting bandwidth. I fixed this by taking the max of 1 cycle and the
payloadDelay instead, however, I’m unsure if this is correct.
From: Mahyar Samani via gem5-users <gem5-users@gem5.org>
Sent: October 20, 2020 8:59 AM
To: gem5 users mailing list <gem5-users@gem5.org>
Cc: Mahyar Samani <msam...@ucdavis.edu>
Subject: [gem5-users] Re: XBar on dcache port impacting BW?
Hey Fisher,
The XBar can at maximum deliver a bandwidth equivalent to 1 packet size (which
I believe is 64 bytes) per cycle (e.g. if the clk_freq is set to 1GHz, it will
at max deliver 64GBps). Does this information comply with the results you are
seeing?
Best Regards,
On Tue, Oct 13, 2020 at 10:50 AM fisher.xue--- via gem5-users
<gem5-users@gem5.org<mailto:gem5-users@gem5.org>> wrote:
I am trying to connect the L1D to the CPU dcache port over an XBar (I intend to
connect another memory to this XBar), however, when making this connection, I
observe that the bandwidth to my L1 halves due to XBar contention, however, I
am modelling this as a 0-latency XBar with effectively infinite width. Does
anyone have any idea what I could be doing wrong?
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Mahyar Samani (he/him/his)
Electrical and Computer Engineering Department
Research Assistant at DArchR<https://arch.cs.ucdavis.edu/> (2235 Kemper Hall)
Secretary
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Vice President
Iranian Student Association at UC Davis
University of California, Davis
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