Hey Fisher, The XBar can at maximum deliver a bandwidth equivalent to 1 packet size (which I believe is 64 bytes) per cycle (e.g. if the clk_freq is set to 1GHz, it will at max deliver 64GBps). Does this information comply with the results you are seeing?
Best Regards, On Tue, Oct 13, 2020 at 10:50 AM fisher.xue--- via gem5-users < gem5-users@gem5.org> wrote: > I am trying to connect the L1D to the CPU dcache port over an XBar (I > intend to connect another memory to this XBar), however, when making this > connection, I observe that the bandwidth to my L1 halves due to XBar > contention, however, I am modelling this as a 0-latency XBar with > effectively infinite width. Does anyone have any idea what I could be doing > wrong? > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > -- Mahyar Samani (he/him/his) Electrical and Computer Engineering Department Research Assistant at *DArchR <https://arch.cs.ucdavis.edu/> (*2235 Kemper Hall) Secretary ECE-GSA Vice President Iranian Student Association at UC Davis University of California, Davis
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