Hello Kazi,
Can you direct me on how I can reproduce the error you are getting? Can you
please answer the following questions?
- What script are you running?
- What command are you using?
- What version of gem5 are you using (which commit/branch)?
- Did you build gem5 with DRAMSim3?
Best Regards,
On Tue, Mar 15, 2022 at 3:34 PM Kazi Asifuzzaman <kazi.asifuzza...@gmail.com>
wrote:
> Hi Mahyar,
>
> Thanks for the suggestions. I applied them as well as updating the
> directory paths for the config files. Now it throws the exception from this
> segment. how should we define the range of the memory? Any ideas?
>
> @overrides(AbstractMemorySystem)
> def set_memory_range(self, ranges: List[AddrRange]) -> None:
> if len(ranges) != 1 or ranges[0].size != self._size:
> raise Exception(
> "Single channel DRAMSim memory controller requires a
> single "
> "range which matches the memory's size."
> )
> self.mem_ctrl.range = ranges[0]
>
> Thanks,
>
> Kazi
>
> On Mon, Mar 14, 2022 at 5:27 PM Mahyar Samani <msam...@ucdavis.edu> wrote:
>
>> Hello Kazi,
>>
>> I looked at the script and you should make the following changes:
>>
>> from gem5.components.memory import SingleChannelDDR3_1600 --> from
>> gem5.components.memory.dramsim_3 import SingleChannelDDR3_1600
>> requires(isa_required=ISA.ARM) --> requires(isa_required=ISA.X86), if it
>> does not work comment out for now
>> memory = SingleChannelDDR3_1600(size="32MB") --> No Change needed
>> from gem5.resources.resource import Resource (line 49 in the original
>> file) --> from gem5.resources.resource import CustomResource
>> Resource("arm-hello64-static") --> CustomResource(local_path=[the path
>> to your binary])
>>
>> Best Regards,
>>
>>
>> On Mon, Mar 14, 2022 at 1:54 PM Kazi Asifuzzaman <
>> kazi.asifuzza...@gmail.com> wrote:
>>
>>> Hi Mahyar,
>>>
>>> I am trying to prepare a SE mode for x86. To replicate the ARM config
>>> for this, could you please clarify how do I replace the parts in RED:
>>>
>>> from gem5.components.memory import SingleChannelDDR3_1600 //For using
>>> DRAMsim3. How do I specify the memory config *from* DRAMsim3 (e.g.
>>> DDR3-1600)
>>> requires(isa_required=ISA.ARM) //Any check
>>> for x86 ISA ?
>>> memory = SingleChannelDDR3_1600(size="32MB") //Again,
>>> how do I specify a specific memory protocol to be used *from* DRAMsim3
>>> Resource("arm-hello64-static") //if I want
>>> to use a binary from a directory
>>>
>>> Thanks,
>>>
>>> *Kazi*
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>> On Mon, Mar 7, 2022 at 4:57 PM Mahyar Samani <msam...@ucdavis.edu>
>>> wrote:
>>>
>>>> Hello Kazi,
>>>>
>>>> Take a look at configs/example/gem5_library/arm-hello.py. It is a good
>>>> example of SE mode for ARM ISA. If you are interested in instantiating a
>>>> memory module look at lines 47, and 62 from the same file.
>>>> P.S. I'm checking out the stable branch on the gem5 repo
>>>> (Hash: 141cc37c2d4b93959d4c249b8f7e6a8b2ef75338).
>>>>
>>>> Best Regards,
>>>>
>>>> On Mon, Mar 7, 2022 at 1:17 PM Kazi Asifuzzaman <
>>>> kazi.asifuzza...@gmail.com> wrote:
>>>>
>>>>> Hi Mahyar,
>>>>>
>>>>> Thanks for your mail and suggestions. Could you please give examples
>>>>> of:
>>>>> 1. How to use gem5 standard library to configure a system, instead of
>>>>> using se.py?
>>>>> 2. How to use standard library API to instantiate a memory?
>>>>>
>>>>> Thanks,
>>>>>
>>>>> Kazi
>>>>>
>>>>> On Fri, Mar 4, 2022 at 1:43 PM Mahyar Samani <msam...@ucdavis.edu>
>>>>> wrote:
>>>>>
>>>>>> Hello Kazi,
>>>>>>
>>>>>> Thanks for reaching out. Yes, I am aware of the problem. Fortunately,
>>>>>> the issue is not with gem5/DRAMSim3 integration. Rather, it's just caused
>>>>>> by some of the differences between gem5 and DRAMSim3 memory controller. I
>>>>>> assume you are using either of the se.py or fs.py in src/config/example.
>>>>>> I
>>>>>> can propose a quick solution to your problem. However, we believe using
>>>>>> se.py/fs.py to do your simulation is not the best solution. We have
>>>>>> recently added the gem5 standard library that makes it easier for you to
>>>>>> configure the system you want to simulate. Back to the solution, fs.py
>>>>>> and
>>>>>> se.py use api from src/config/common/MemConfig.py to configure the memory
>>>>>> components in the system (this does not include caches). What you'll need
>>>>>> to do (reminder: this a quick solution) is to find calls to api from
>>>>>> MemConfig.py in se.py/fs.py (whichever one you are using) and remove
>>>>>> those calls and instantiate the memory yourself. The standard library
>>>>>> has a
>>>>>> really easy api to instantiate a memory. Please look at
>>>>>> src/python/gem5/components/memory/dramsim_3.py for memories from
>>>>>> DRAMSim3.
>>>>>> I hope this is helpfull, if you needed further help, please feel free to
>>>>>> reach out to me (I have a deadline today at 11:59 pm PST and will respond
>>>>>> asap after that). I would appreciate it if you could send your questions
>>>>>> to
>>>>>> the gem5 mailing list. This way, other people would also be aware of the
>>>>>> bugs and inconsistencies in the repo and it definitely makes it a bigger
>>>>>> priority to be solved. Feel free to cc me so I make sure to respond as
>>>>>> quickly as possible.
>>>>>>
>>>>>> Best Regards,
>>>>>>
>>>>>> On Fri, Mar 4, 2022 at 10:23 AM Kazi Asifuzzaman <
>>>>>> kazi.asifuzza...@gmail.com> wrote:
>>>>>>
>>>>>>> Good Afternoon Mahyar,
>>>>>>>
>>>>>>> From a gem5 discussion group, it appears that you are managing (a
>>>>>>> part of) the gem5 project. I am trying to integrate Gem5 with DRAMSim3
>>>>>>> (the
>>>>>>> way it explains in ext/dramsim3/README), but when the try to use
>>>>>>> --mem-type=DRAMsim3 to run the simulation it says: AttributeError:
>>>>>>> object 'DRAMsim3' has no attribute 'controller'
>>>>>>>
>>>>>>> Could you please shed some light on it? In a mail thread I see that
>>>>>>> you were working on a fix for this, could you resolve this issue?
>>>>>>>
>>>>>>> Many thanks for your time,
>>>>>>>
>>>>>>> *Kazi *
>>>>>>>
>>>>>>
>>>>>>
>>>>>> --
>>>>>> Mahyar Samani
>>>>>> PhD Student
>>>>>> Research Assistant at *DArchR <https://arch.cs.ucdavis.edu/>*
>>>>>> University of California, Davis
>>>>>> May the Force be with you.
>>>>>>
>>>>>
>>>>
>>>> --
>>>> Mahyar Samani
>>>> PhD Student
>>>> Research Assistant at *DArchR <https://arch.cs.ucdavis.edu/>*
>>>> University of California, Davis
>>>> May the Force be with you.
>>>>
>>>
>>
>> --
>> Mahyar Samani
>> PhD Student
>> Research Assistant at *DArchR <https://arch.cs.ucdavis.edu/>*
>> University of California, Davis
>> May the Force be with you.
>>
>
--
Mahyar Samani
PhD Student
Research Assistant at *DArchR <https://arch.cs.ucdavis.edu/>*
University of California, Davis
May the Force be with you.
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