On 3/22/2023 12:09 PM, Priyanka Ankolekar via gem5-users wrote:
Regarding the other part of your email:
Let me begin by saying I am a novice to both RISCV and gem5.
I have a RISCVÂ RTL with a certain config. I have set up gem5 to match that configuration. I want to
make sure that they are indeed equivalent so that I can run some experiments on gem5 (instead of on
RTL) since that would be faster and easier. In order to establish that equivalence, I am running a
simple benchmark test on both RTL and gem5. The final numbers like DMIPS/MHz etc match fairly
closely. But I want to dig further to see if the retired instruction/s at a given tick, for both
these setups, are also a close match.
Hence the questions.
My suggestion would be to:
- Read the CSR at points of interest - one hopes not *too* many points to avoid being overwhelmed
with output. Do this in gem5 and in your RTL.
- Add code to gem5 to print the value the tick and the value read when the CSR is read. A DNPRINTF
call would serve nicely. grep can help you find where the right code is using the register name.
Would this do the trick?
Best - EM
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