Unfortunately, I don't think there's an easy answer. You could put a finite write buffer in main memory, but the only current way to provide backpressure when it fills up is through bus flow control, which would stall reads as well as writes. Another approach is to add the ability to nack writebacks at the protocol level, but that's a pretty significant change to a pretty complex and fragile part of the system.
This fragility is a big part of the reason we're moving away from the "classic" M5 memory system to Ruby... I don't know what the writeback bandwidth modeling is like in Ruby, but I'm sure it's at least as good :-), and even if it's not what you need, it might be easier to enhance. So overall your easiest path may well be to switch to Ruby. Steve On Mon, Jul 5, 2010 at 8:34 AM, sheng qiu <[email protected]> wrote: > Hi Steve, > > Thanks for your answer. if i want to include the effect of writeback latency > to memory into the running application(i.e. the bus bandwidth is not > enough), what can i do for this? > > Thanks, > Sheng > > > _______________________________________________ > m5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/m5-users > _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
