hi Steve, Thank you very much for your patient. i may not state my doubt clearly. I expect if the writeback take up the memory bus longer than usual, then the read request maybe delayed by lack of memory bus bandwidth. So the total sim_ticks may be larger. i just want to know whether M5 include this impact. That's why i expected that set latency larger for pkt->iswrite() may lead larger sim_ticks than original. So maybe i misunderstand this latency? Or can you tell me where i can find the relevant codes of this part?
Thanks, Sheng
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