From: Josh Grebe <[EMAIL PROTECTED]>
Date: Wed, 29 Jun 2005 12:34:27 -0500
> I'm sorry to say that I still crash reliably with this patch. Just
> to recap, it is a netra 1405, 4x440, 1G ram. Crashed after about 30
> minutes of running my disk-loading crashme.sh.
Thanks for testing...
Hmmm, so what else fundamentally changed in 2.6.x vs. 2.4.x
sparc64 wise? One thing that sticks out is that we do batched
TLB flushing now. That's kind of tricky to get right because
UltraSPARC requires that one does a "membar #Sync" or
"flush" after any internal cpu register store before any
subsequent non-internal load or store is performed.
We're slightly violating that in the new batched TLB flushing
code. So it's worth trying the patch below out.
This goes on top of the membar patch, and the UltraSPARC-III
fix for the membar patch. If there are some rejects, they'll
be minor and easy to fix up.
Let me know if this patch makes any difference.
[SPARC64]: Add missing "membar #Sync" to flush_tlb_pending().
flush_tlb_pending() (both the spitfire and cheetah variants)
need to do a membar after writing the context register, before
we load the first PTE entry in the batch array.
Signed-off-by: David S. Miller <[EMAIL PROTECTED]>
diff --git a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S
--- a/arch/sparc64/mm/ultra.S
+++ b/arch/sparc64/mm/ultra.S
@@ -57,6 +57,7 @@ __flush_tlb_pending:
mov SECONDARY_CONTEXT, %o4
ldxa [%o4] ASI_DMMU, %g2
stxa %o0, [%o4] ASI_DMMU
+ membar #Sync
1: sub %o1, (1 << 3), %o1
ldx [%o2 + %o1], %o3
andcc %o3, 1, %g0
@@ -250,7 +251,7 @@ __cheetah_flush_tlb_mm: /* 15 insns */
retl
wrpr %g7, 0x0, %pstate
-__cheetah_flush_tlb_pending: /* 23 insns */
+__cheetah_flush_tlb_pending: /* 24 insns */
/* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
rdpr %pstate, %g7
sllx %o1, 3, %o1
@@ -260,6 +261,7 @@ __cheetah_flush_tlb_pending: /* 23 insns
mov PRIMARY_CONTEXT, %o4
ldxa [%o4] ASI_DMMU, %g2
stxa %o0, [%o4] ASI_DMMU
+ membar #Sync
1: sub %o1, (1 << 3), %o1
ldx [%o2 + %o1], %o3
andcc %o3, 1, %g0
@@ -318,7 +320,7 @@ cheetah_patch_cachetlbops:
sethi %hi(__cheetah_flush_tlb_pending), %o1
or %o1, %lo(__cheetah_flush_tlb_pending), %o1
call cheetah_patch_one
- mov 23, %o2
+ mov 24, %o2
#ifdef DCACHE_ALIASING_POSSIBLE
sethi %hi(__flush_dcache_page), %o0
@@ -367,6 +369,7 @@ xcall_flush_tlb_pending:
mov PRIMARY_CONTEXT, %g4
ldxa [%g4] ASI_DMMU, %g2
stxa %g5, [%g4] ASI_DMMU
+ membar #Sync
1: sub %g1, (1 << 3), %g1
ldx [%g7 + %g1], %g5
andcc %g5, 0x1, %g0
--
[email protected] mailing list
