I have a strange result with this code, is it a bug of GHDL or a VHDL
standard "feature" ?
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
entity test is
end entity;
architecture t of test is
signal a:std_logic_vector(15 downto 0);
begin
P:process
--copy v into a
procedure p(v:std_logic_vector)is
begin
a<=v;
end procedure;
begin
p((15=>'1',14 downto 0=>'0'));
wait;
end process;
--dump a on change
Q:process(a)
begin
for i in a'range loop
write(OUTPUT,"a(" & integer'image(i) & ") = " &
std_logic'image(a(i)));
end loop;
end process;
end architecture;
$ ghdl -r test
a(15) = 'U'
a(14) = 'U'
a(13) = 'U'
a(12) = 'U'
a(11) = 'U'
a(10) = 'U'
a(9) = 'U'
a(8) = 'U'
a(7) = 'U'
a(6) = 'U'
a(5) = 'U'
a(4) = 'U'
a(3) = 'U'
a(2) = 'U'
a(1) = 'U'
a(0) = 'U'
a(15) = '0'
a(14) = '0'
a(13) = '0'
a(12) = '0'
a(11) = '0'
a(10) = '0'
a(9) = '0'
a(8) = '0'
a(7) = '0'
a(6) = '0'
a(5) = '0'
a(4) = '0'
a(3) = '0'
a(2) = '0'
a(1) = '0'
a(0) = '1'
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