Tristan Gingold a écrit : > On Thu, Oct 08, 2009 at 10:28:04PM +0200, Sylvere Teissier wrote: >> I have a strange result with this code, is it a bug of GHDL or a VHDL >> standard "feature" ? > > Looks correct. The first dump occurs at initialization, the second one > when a has changed. > > What did you expect ? > > Tristan. >
the vector is reversed With (15=>'1',14 downto 0=>'0'), I expected: a(15) = '1' a(14) = '0' a(13) = '0' a(12) = '0' a(11) = '0' a(10) = '0' a(9) = '0' a(8) = '0' a(7) = '0' a(6) = '0' a(5) = '0' a(4) = '0' a(3) = '0' a(2) = '0' a(1) = '0' a(0) = '0' instead of: a(15) = '0' a(14) = '0' a(13) = '0' a(12) = '0' a(11) = '0' a(10) = '0' a(9) = '0' a(8) = '0' a(7) = '0' a(6) = '0' a(5) = '0' a(4) = '0' a(3) = '0' a(2) = '0' a(1) = '0' a(0) = '1' _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
