On Fri, Oct 09, 2009 at 09:38:51AM +0200, Sylvere Teissier wrote: > Tristan Gingold a écrit : > > On Thu, Oct 08, 2009 at 10:28:04PM +0200, Sylvere Teissier wrote: > >> I have a strange result with this code, is it a bug of GHDL or a VHDL > >> standard "feature" ? > > > > Looks correct. The first dump occurs at initialization, the second one > > when a has changed. > > > > What did you expect ? > > > > Tristan. > > > > the vector is reversed > > With (15=>'1',14 downto 0=>'0'), I expected:
Hi, in fact I think that ghdl is right. The aggregate is used here: p((15=>'1',14 downto 0=>'0')); According to LRM93, 7.3.2.2: The bounds of an array that does not have an others choice are determined as follows: [...]; otherwise, the direction of the index subtype of the aggrgate is that of the index subtype of the base type of the aggregate. As the base type is std_logic_vector, the direction is to. I agree that this is counter-intuitive, but that how VHDL is defined. Thanks, Tristan. _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
