with
-Plibs/unisim looks better.
At the moment I have undefined state. I have to proof my code if I have
a bug or the warnings are my problem.
Rene
./../../src/synopsys/std_logic_arith.vhdl:391:14:warning: function
"left_signed_arg" is never referenced
../../../src/synopsys/std_logic_arith.vhdl:400:14:warning: function
"left_unsigned_arg" is never referenced
../../../src/synopsys/std_logic_arith.vhdl:409:14:warning: function
"mult_signed_arg" is never referenced
../../../src/synopsys/std_logic_arith.vhdl:418:14:warning: function
"mult_unsigned_arg" is never referenced
../../../src/synopsys/std_logic_arith.vhdl:1258:14:warning: function
"unsigned_return_boolean" is never referenced
../../../src/synopsys/std_logic_arith.vhdl:1266:14:warning: function
"signed_return_boolean" is never referenced
../rtl/VGA1024_768.vhd:50:4:warning: component instance
"clkin_ibufg_inst" is not bound
../rtl/VGA1024_768.vhd:33:14:warning: (in default configuration of
vgatest(behavioral))
../rtl/VGA1024_768.vhd:54:4:warning: component instance "clk0_bufg_inst"
is not bound
../rtl/VGA1024_768.vhd:33:14:warning: (in default configuration of
vgatest(behavioral))
../rtl/VGA1024_768.vhd:60:4:warning: component instance
"clkfx_bufg_inst" is not bound
../rtl/VGA1024_768.vhd:33:14:warning: (in default configuration of
vgatest(behavioral))
../rtl/VGA1024_768.vhd:65:3:warning: component instance "dcm_sp_inst" is
not bound
../rtl/VGA1024_768.vhd:33:14:warning: (in default configuration of
vgatest(behavioral))
analyze ../rtl/tb_vga.vhd
analyze /opt/Xilinx/11.1/ISE/vhdl/src/unisims/unisim_VCOMP.vhd
analyze ../rtl/VGA1024_768.vhd
../rtl/VGA1024_768.vhd:50:4:warning: no default binding for
instantiation of component "ibufg"
/opt/Xilinx/11.1/ISE/vhdl/src/unisims/unisim_VCOMP.vhd:6704:11:warning:
visible declaration for ibufg is component "ibufg"
/opt/Xilinx/11.1/ISE/vhdl/src/unisims/unisim_VCOMP.vhd:6704:11:warning:
no entity "ibufg" in library "unisim"
../rtl/VGA1024_768.vhd:54:4:warning: no default binding for
instantiation of component "bufg"
/opt/Xilinx/11.1/ISE/vhdl/src/unisims/unisim_VCOMP.vhd:544:11:warning:
visible declaration for bufg is component "bufg"
/opt/Xilinx/11.1/ISE/vhdl/src/unisims/unisim_VCOMP.vhd:544:11:warning:
no entity "bufg" in library "unisim"
../rtl/VGA1024_768.vhd:60:4:warning: no default binding for
instantiation of component "bufg"
/opt/Xilinx/11.1/ISE/vhdl/src/unisims/unisim_VCOMP.vhd:544:11:warning:
visible declaration for bufg is component "bufg"
/opt/Xilinx/11.1/ISE/vhdl/src/unisims/unisim_VCOMP.vhd:544:11:warning:
no entity "bufg" in library "unisim"
../rtl/VGA1024_768.vhd:65:3:warning: no default binding for
instantiation of component "dcm_sp"
/opt/Xilinx/11.1/ISE/vhdl/src/unisims/unisim_VCOMP.vhd:1631:11:warning:
visible declaration for dcm_sp is component "dcm_sp"
/opt/Xilinx/11.1/ISE/vhdl/src/unisims/unisim_VCOMP.vhd:1631:11:warning:
no entity "dcm_sp" in library "unisim"
elaborate
tb_vga
../rtl/VGA1024_768.vhd:50:4:warning: component instance
"clkin_ibufg_inst" is not bound
../rtl/VGA1024_768.vhd:33:14:warning: (in default configuration of
vgatest(behavioral))
../rtl/VGA1024_768.vhd:54:4:warning: component instance "clk0_bufg_inst"
is not bound
../rtl/VGA1024_768.vhd:33:14:warning: (in default configuration of
vgatest(behavioral))
../rtl/VGA1024_768.vhd:60:4:warning: component instance
"clkfx_bufg_inst" is not bound
../rtl/VGA1024_768.vhd:33:14:warning: (in default configuration of
vgatest(behavioral))
../rtl/VGA1024_768.vhd:65:3:warning: component instance "dcm_sp_inst" is
not bound
../rtl/VGA1024_768.vhd:33:14:warning: (in default configuration of
vgatest(behavioral))
Am Dienstag, den 12.01.2010, 12:37 +0000 schrieb ALEX HUNTLEY:
> I think when you're compiling your design, ghdl is not finding the
> unisim library. Try adding "-Plibs/unisim" to the make a design
> instructio, i.e.:
>
> ghdl -m -g -Plibs/unisim --workdir=libs/work --warn-default-binding
> --warn-binding --warn-library --warn-body --warn-specs --warn-unused
> $2
>
> Not sure but you may need to do the same for the ghdl -r command.
>
> Hope this helps.
>
> Alex
>
> 2010/1/12 René Doß <[email protected]>
> I have ubuntu 9.10 32bit and ISE 11.4.
> I change from 64bit to 32 bit system.
>
> Now I have some Xilinx specific parts in my VHDL code.
>
> I tried the simulation similary the skripts.
> http://aoa.vwthunderstorm.de/wiki/FPGA_Linux_Simulation
>
> I got everytime an error.
>
> r...@pc-black:~/FPGA/VHDL/VGA1024_768/sim/sim/scr$ make
> ./simulate.sh vga tb_vga
> compile xilinx unisim libraries
> compile design files
> make a design
> ../rtl/VGA1024_768.vhd:19:9: cannot find resource library
> "unisim"
>
>
> I have read, that somebody managed a simulation also with this
> library.
>
>
> Has anybody some suggestions??
>
>
> Thank you.
>
> Rne
>
>
> _______________________________________________
> Ghdl-discuss mailing list
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>
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