First thank you Tristan for you simulation test.
> I have tried your design in attachment with ghdl. I can simulate it without
> issue.
> Which entity isn't found by ghdl ?
>
> Tristan.
>
--------------------------------------------------------------------------------
My GHDL Version:
ghdl -v
GHDL 0.28 (20090917) [Sokcho edition]
Compiled with GNAT Version: GPL 2008 (20080521)
GCC back-end code generator
Written by Tristan Gingold.
----------------------------------------------------------------------------------
When I look in GTKWave:
My stimulation clock clk50_in has a valid clock signal. All clocks from
DCM has undefined signal.
Also I note. Ghld create a file sim/libs/unisim/unisim-obj93.cf
This file is readable ascii table. I miss on it the vhdl files from the
subfolder unisims/primitive !?
The models buffer and DCM are in the file unisims/primitive/autobuf.vhd
and in unisims/primitive/dcm.vhd
I think the problem is this subfolder. I tried out to analyze this
folder but the correct sequence is needed.
The output from ghdl.
----------------------------------------------------------------------------------
sim/scr$ sudo make
./simulate.sh vga tb_vga
compile xilinx unisim libraries
compile design files
make a design
../../../src/synopsys/std_logic_arith.vhdl:391:14:warning: function
"left_signed_arg" is never referenced
../../../src/synopsys/std_logic_arith.vhdl:400:14:warning: function
"left_unsigned_arg" is never referenced
../../../src/synopsys/std_logic_arith.vhdl:409:14:warning: function
"mult_signed_arg" is never referenced
../../../src/synopsys/std_logic_arith.vhdl:418:14:warning: function
"mult_unsigned_arg" is never referenced
../../../src/synopsys/std_logic_arith.vhdl:1258:14:warning: function
"unsigned_return_boolean" is never referenced
../../../src/synopsys/std_logic_arith.vhdl:1266:14:warning: function
"signed_return_boolean" is never referenced
../rtl/VGA1024_768.vhd:51:4:warning: component instance
"clkin_ibufg_inst" is not bound
../rtl/VGA1024_768.vhd:34:14:warning: (in default configuration of
vgatest(behavioral))
../rtl/VGA1024_768.vhd:55:4:warning: component instance "clk0_bufg_inst"
is not bound
../rtl/VGA1024_768.vhd:34:14:warning: (in default configuration of
vgatest(behavioral))
../rtl/VGA1024_768.vhd:61:4:warning: component instance
"clkfx_bufg_inst" is not bound
../rtl/VGA1024_768.vhd:34:14:warning: (in default configuration of
vgatest(behavioral))
../rtl/VGA1024_768.vhd:66:3:warning: component instance "dcm_sp_inst" is
not bound
../rtl/VGA1024_768.vhd:34:14:warning: (in default configuration of
vgatest(behavioral))
analyze ../rtl/tb_vga.vhd
analyze /opt/Xilinx/11.1/ISE/vhdl/src/unisims/unisim_VCOMP.vhd
analyze ../rtl/VGA1024_768.vhd
../rtl/VGA1024_768.vhd:51:4:warning: no default binding for
instantiation of component
"ibufg"
/opt/Xilinx/11.1/ISE/vhdl/src/unisims/unisim_VCOMP.vhd:6704:11:warning:
visible declaration for ibufg is component
"ibufg"
/opt/Xilinx/11.1/ISE/vhdl/src/unisims/unisim_VCOMP.vhd:6704:11:warning:
no entity "ibufg" in library
"unisim"
../rtl/VGA1024_768.vhd:55:4:warning: no default binding for
instantiation of component
"bufg"
/opt/Xilinx/11.1/ISE/vhdl/src/unisims/unisim_VCOMP.vhd:544:11:warning:
visible declaration for bufg is component "bufg"
/opt/Xilinx/11.1/ISE/vhdl/src/unisims/unisim_VCOMP.vhd:544:11:warning:
no entity "bufg" in library "unisim"
../rtl/VGA1024_768.vhd:61:4:warning: no default binding for
instantiation of component "bufg"
/opt/Xilinx/11.1/ISE/vhdl/src/unisims/unisim_VCOMP.vhd:544:11:warning:
visible declaration for bufg is component "bufg"
/opt/Xilinx/11.1/ISE/vhdl/src/unisims/unisim_VCOMP.vhd:544:11:warning:
no entity "bufg" in library "unisim"
../rtl/VGA1024_768.vhd:66:3:warning: no default binding for
instantiation of component "dcm_sp"
/opt/Xilinx/11.1/ISE/vhdl/src/unisims/unisim_VCOMP.vhd:1631:11:warning:
visible declaration for dcm_sp is component "dcm_sp"
/opt/Xilinx/11.1/ISE/vhdl/src/unisims/unisim_VCOMP.vhd:1631:11:warning:
no entity "dcm_sp" in library "unisim"
elaborate tb_vga
../rtl/VGA1024_768.vhd:51:4:warning: component instance
"clkin_ibufg_inst" is not bound
../rtl/VGA1024_768.vhd:34:14:warning: (in default configuration of
vgatest(behavioral))
../rtl/VGA1024_768.vhd:55:4:warning: component instance "clk0_bufg_inst"
is not bound
../rtl/VGA1024_768.vhd:34:14:warning: (in default configuration of
vgatest(behavioral))
../rtl/VGA1024_768.vhd:61:4:warning: component instance
"clkfx_bufg_inst" is not bound
../rtl/VGA1024_768.vhd:34:14:warning: (in default configuration of
vgatest(behavioral))
../rtl/VGA1024_768.vhd:66:3:warning: component instance "dcm_sp_inst" is
not bound
../rtl/VGA1024_768.vhd:34:14:warning: (in default configuration of
vgatest(behavioral))
==================================
design consists of following units:
----------------------------------
entity vgatest
architecture behavioral of vgatest
entity tb_vga
architecture behavior of tb_vga
====================================
detected following design hierarchy:
------------------------------------
run the testbench
tb_vga [entity]
`-behavior [arch]
`-uut [instance]
`-vgatest [entity]
`-behavioral [arch]
+-clkin_ibufg_inst [instance]
+-clk0_bufg_inst [instance]
+-clkfx_bufg_inst [instance]
`-dcm_sp_inst [instance]
std.standard [package]
ieee.std_logic_1164 [package]
ieee.std_logic_arith [package]
ieee.std_logic_unsigned [package]
ieee.numeric_std [package]
unisim.vcomponents [package]
./tb_vga:info: simulation stopped by --stop-time
gtkwave ../waveform/vga.ghw
GTKWave Analyzer v3.3.0 (w)1999-2009 BSI
[0] start time.
[2000000000] end time.
Warning: encountered 1 glitch across 1 glitch region.
^Cmake: *** [wave] Interrupt
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