I can not simulate with ghdl but with isim. Ghdl can not found some entity from unisim.
How can I make possible that ghdl can connect these modules correctly? I have my VHDl code in the attachment. Thank you. Rene Am Dienstag, den 12.01.2010, 12:37 +0000 schrieb ALEX HUNTLEY: > I think when you're compiling your design, ghdl is not finding the > unisim library. Try adding "-Plibs/unisim" to the make a design > instructio, i.e.: > > ghdl -m -g -Plibs/unisim --workdir=libs/work --warn-default-binding > --warn-binding --warn-library --warn-body --warn-specs --warn-unused > $2 > > Not sure but you may need to do the same for the ghdl -r command. > > Hope this helps. > > Alex > > 2010/1/12 René Doß <d...@gmx.de> > I have ubuntu 9.10 32bit and ISE 11.4. > I change from 64bit to 32 bit system. > > Now I have some Xilinx specific parts in my VHDL code. > > I tried the simulation similary the skripts. > http://aoa.vwthunderstorm.de/wiki/FPGA_Linux_Simulation > > I got everytime an error. > > r...@pc-black:~/FPGA/VHDL/VGA1024_768/sim/sim/scr$ make > ./simulate.sh vga tb_vga > compile xilinx unisim libraries > compile design files > make a design > ../rtl/VGA1024_768.vhd:19:9: cannot find resource library > "unisim" > > > I have read, that somebody managed a simulation also with this > library. > > > Has anybody some suggestions?? > > > Thank you. > > Rne > > > _______________________________________________ > Ghdl-discuss mailing list > Ghdl-discuss@gna.org > https://mail.gna.org/listinfo/ghdl-discuss > > _______________________________________________ > Ghdl-discuss mailing list > Ghdl-discuss@gna.org > https://mail.gna.org/listinfo/ghdl-discuss
#--------------------------------------------------------------------
DESIGN = vga
TB = tb_${DESIGN}
#rule for whole simulation
sim : ../waveform/$(DESIGN).ghw wave
../waveform/$(DESIGN).ghw : ../../rtl/*.vhd
./simulate.sh $(DESIGN) $(TB)
wave : ../waveform/$(DESIGN).ghw
gtkwave ../waveform/$(DESIGN).ghw
all : clean sim
#rule for cleaning
clean :
rm -rf sim;
cd ../waveform && rm -rf *;
cd ../libs && rm -rf *;
#-----------------------------------------------
simulate.sh
Description: application/shellscript
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:50:54 01/06/2010
-- Design Name:
-- Module Name: /home/red/FPGA/VHDL/VGA1024_768/tb_vga.vhd
-- Project Name: VGA1024_768
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: vgatest
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_vga IS
END tb_vga;
ARCHITECTURE behavior OF tb_vga IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT vgatest
PORT(
clk50_in : IN std_logic;
CLK0_OUT : OUT std_logic;
red_out : OUT std_logic;
green_out : OUT std_logic;
blue_out : OUT std_logic;
hs_out : OUT std_logic;
vs_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk50_in : std_logic := '0';
--Outputs
signal CLK0_OUT : std_logic;
signal red_out : std_logic;
signal green_out : std_logic;
signal blue_out : std_logic;
signal hs_out : std_logic;
signal vs_out : std_logic;
-- Clock period definitions
constant clk50_in_period : time := 10 ns;
constant CLK0_OUT_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: vgatest PORT MAP (
clk50_in => clk50_in,
CLK0_OUT => CLK0_OUT,
red_out => red_out,
green_out => green_out,
blue_out => blue_out,
hs_out => hs_out,
vs_out => vs_out
);
-- Clock process definitions
clk50_in_process :process
begin
clk50_in <= '0';
wait for clk50_in_period/2;
clk50_in <= '1';
wait for clk50_in_period/2;
end process;
CLK0_OUT_process :process
begin
CLK0_OUT <= '0';
wait for CLK0_OUT_period/2;
CLK0_OUT <= '1';
wait for CLK0_OUT_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ms.
wait for 100 ms;
wait for clk50_in_period*10;
-- insert stimulus here
wait;
end process;
END;
-- Additional Comments:
--
-- Pin Assignment:
-- MET clk50_in loc = T9
-- NET red_out LOC=R12;
-- NET green_out LOC=T12;
-- NET blue_out LOC=R11;
-- NET hs_out LOC=R9;
-- NET vs_out LOC=T10;
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity vgatest is
port(clk50_in : in std_logic;
CLK0_OUT : out std_logic;
red_out : out std_logic;
green_out : out std_logic;
blue_out : out std_logic;
hs_out : out std_logic;
vs_out : out std_logic);
end vgatest;
architecture behavioral of vgatest is
signal clk75 : std_logic;
signal CLK0_BUF : std_logic;
signal CLKFB_IN : std_logic;
signal hcounter : integer range 0 to 1328;
signal vcounter : integer range 0 to 806;
signal color: std_logic_vector(2 downto 0):="111";
signal CLKIN_IBUFG : std_logic;
signal CLKFX_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLK50_in,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLK75);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 2,
CLKFX_MULTIPLY => 3,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>'0',
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>open,
PSDONE=>open,
STATUS=>open);
-- change color every one second
p1: process (clk75)
variable cnt: integer;
begin
if clk75'event and clk75='1' then
cnt := cnt + 1;
if cnt = 25000000 then
color <= color + "001";
cnt := 0;
end if;
end if;
end process;
p2: process (clk75, hcounter, vcounter)
variable x: integer range 0 to 2000:=0;
variable y: integer range 0 to 2000:=0;
begin
-- hcounter counts from 0 to 799
-- vcounter counts from 0 to 520
-- x coordinate: 0 - 639 (x = hcounter - 144, i.e., hcounter -Tpw-Tbp)
-- y coordinate: 0 - 479 (y = vcounter - 31, i.e., vcounter-Tpw-Tbp)
x := hcounter ;
y := vcounter ;
if clk75'event and clk75 = '1' then
-- To draw a pixel in (x0, y0), simply test if the ray trace to it
-- and set its color to any value between 1 to 7. The following example simply sets
-- the whole display area to a single-color wash, which is changed every one
-- second.
if x < 1023 and y < 767 then
red_out <= color(0);
green_out <= color(1);
blue_out <= color(2);
else
-- if not traced, set it to "black" color
red_out <= '0';
green_out <= '0';
blue_out <= '0';
end if;
-- Here is the timing for horizontal synchronization.
-- (Refer to p. 24, Xilinx, Spartan-3 Starter Kit Board User Guide)
-- Pulse width: Tpw = 96 cycles @ 25 MHz
-- Back porch: Tbp = 48 cycles
-- Display time: Tdisp = 640 cycles
-- Front porch: Tfp = 16 cycles
-- Sync pulse time (total cycles) Ts = 800 cycles
if hcounter > 1047 and hcounter < 1185 then
hs_out <= '0';
else
hs_out <= '1';
end if;
-- Here is the timing for vertical synchronization.
-- (Refer to p. 24, Xilinx, Spartan-3 Starter Kit Board User Guide)
-- Pulse width: Tpw = 1600 cycles (2 lines) @ 25 MHz
-- Back porch: Tbp = 23200 cycles (29 lines)
-- Display time: Tdisp = 38400 cycles (480 lines)
-- Front porch: Tfp = 8000 cycles (10 lines)
-- Sync pulse time (total cycles) Ts = 416800 cycles (521 lines)
if vcounter > 770 and vcounter < 778 then
vs_out <= '0';
else
vs_out <= '1';
end if;
-- horizontal counts from 0 to 799
hcounter <= hcounter+1;
if hcounter = 1238 then
vcounter <= vcounter+1;
hcounter <= 0;
end if;
-- vertical counts from 0 to 519
if vcounter = 806 then
vcounter <= 0;
end if;
end if;
end process;
end behavioral;
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