On Thu, 2010-11-04 at 17:08 +0100, [email protected] wrote: > As far as i know, in VHDL, > integers have no support for xor, not, and, or, shl, shr... > it does make some kinds of behavioural tests pretty slow > because it forces the use of std_ulogic_vectors.
Plus unsigned nontrapping modulo arithmetic... Tom _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
