On Wed, 24 Nov 2010 10:48:11 +0100, patrick.forums.elec
<[email protected]> wrote:
Could there be (later) a patch to GHDL that provides AND/OR/XOR
to integers so GCC does not have to make a function call
just of one boolean instruction ? (that would have to be
STOP DOING THIS KIND OF OPTIMISATION
1) it's not the kind if thing that should said to people like me,
who rather take this "taboo" as an exciting incitation to try to prove
you wrong.
2) What "kind of optimisation" is "allowed" ? by who ?
3) Your capslock is stuck on.
4) Preventing someone to optimise is just plain wrong.
The layer2/gimple step of gcc is rearranging the code according with
the
target processor. The final is not the one you think.
What do you think I think ?
Have you looked at the real code generated by GHDL ?
I did. Every time a std_(u)logic vector is used, the
involved machine code can becore very hairy.
Which is necessary "by design" because VHDL is powerful
and allows many things. But there are cases when it's not needed
(behavioural simulation) and that is what i want to address.
For instance a one
line function can be automatically inlined, or a loop from 1 to (
static )
5 can be converted into a copied and pasted code.
depends on a lot. a ****ing lot, and your example is NOT generality.
most operations are done by calling "standard functions" which
are generic, use variadic sizes which the compile can't optimise.
On top of that, by design, GHDL (as far as I know) can't inline
functions.
GCC can inline C functions declared as "inline"
but please prove me wrong with an everyday VHDL example.
By this way the code should stay readable and standard, the compiler
is
doing the relevant optimisations.
the compiler is doing the optimisations it can from what it is told to
do.
If the language does not allow simple, basic, elementary operations,
then there is no way the compiler can guess them all.
std_logic based and "arithmetic_based" ( signed, unsigned )
i am NOT speaking about them, but about the "integer" scalar type.
should stay as two separated types ( with casts ).
i agree on that point. But it's not the one i want to discuss.
std_logic have 9 states for the low
level engineering, that already makes things complex for simple logic
functions. The arithmetic based should handle all the arithmetics
considerations, that make some complexity. We can not handle the
product of
all combinaisons.
I do most things in "std_ulogic_vector".
I cast to "signed" only around operations like add or substract.
Integers can add and substract but lack the boolean operators.
so it's NOT possible to "prototype" or draft a behavioural model
without having to deal with the dirty details of the underlying
"electronics".
* This is why there are people who think that SystemC is cool
(bleaaaah)
* This is why people say that VHDL is "slow" :-(
* This is why it takes so long and so many efforts to make
something (a model ?) even a bit complex directly in VHDL
I'm really curious to know what will come out of this thread.
yg
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