On 23/12/2010 12:59, Jean-Christophe Le Lann wrote:
> Hello
> 
> I need your opinion about my interpretation of the following GHDL
> simulation.
> 
> The design is a single-port ram with SYNCHRONOUS read.
> 
> The testbench simply write 5 data (85..89) at (0..4), and then read the
> data in the same order.
> 
> The gtkwave waveforms are perfectly ok w.r.t my expectations.
> 
> My problem is about the text in the terminal :
> 
> test_mem.vhd:70:5:@390ns:(report note): 20-reading memory
> test_mem.vhd:73:7:@390ns:(report note): 20-address 0
> test_mem.vhd:78:7:@410ns:(report note): 21-READ data dout 89
> test_mem.vhd:73:7:@410ns:(report note): 21-address 1
> test_mem.vhd:78:7:@430ns:(report note): 22-READ data dout 85
> test_mem.vhd:73:7:@430ns:(report note): 22-address 2
> test_mem.vhd:78:7:@450ns:(report note): 23-READ data dout 86
> test_mem.vhd:73:7:@450ns:(report note): 23-address 3
> test_mem.vhd:78:7:@470ns:(report note): 24-READ data dout 87
> test_mem.vhd:73:7:@470ns:(report note): 24-address 4
> test_mem.vhd:78:7:@490ns:(report note): 25-READ data dout 88
> 
> We see that at cycle 20 address=0 is generated. ok.
> One cycle later (21), I expected to get the data 85 (as in the
> waveform), but here the message says 89.
> 
> Where am I wrong ?

You set the address at cycle 20
the address is latched by the synchronous memory at cycle 21
the output data is available on "dout" at "cycle 21 + t(access_time)"
so you read it only at cycle 22

-- 
Sylvere Teissier
INVIA
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Le Canet - BP46
13590 Meyreuil
Tel: 04.42.24.50.77
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