On 23/12/2010 14:42, Jean-Christophe Le Lann wrote: > Le 23/12/2010 14:14, Sylvere Teissier a écrit : >> On 23/12/2010 12:59, Jean-Christophe Le Lann wrote: >> >>> Hello >>> >>> We see that at cycle 20 address=0 is generated. ok. >>> One cycle later (21), I expected to get the data 85 (as in the >>> waveform), but here the message says 89. >>> >>> Where am I wrong ? >>> >> You set the address at cycle 20 >> the address is latched by the synchronous memory at cycle 21 >> the output data is available on "dout" at "cycle 21 + t(access_time)" >> so you read it only at cycle 22 >> > Hi Sylvere > > As the design is purely synchronous, the t(access_time) is 0. The > testbench process should see the dout at 21, no ?
yes t(access_time) is 0 but the value aren't updated: you read the value before the rising_edge, just like a flip_flop latch the value just before the rising_edge > > Or a new question : setting the address at cycle 20, how could I read > the data at cycle 21 in the testbench process ? I'm not sure... but a think that adding a delta cycle should do the job: add "wait for 0 ns;" at the end of the function wait_cycles (line 46) this will force the update of the signals changed at cycle 21. > > JCLL > > _______________________________________________ > Ghdl-discuss mailing list > [email protected] > https://mail.gna.org/listinfo/ghdl-discuss > -- Sylvere Teissier INVIA Europarc Sainte Victoire - Bat 6 Le Canet - BP46 13590 Meyreuil Tel: 04.42.24.50.77 ------------------------------- This mail message and attachments (the "message") are solely intended for the addressees. It is confidential in nature . If you receive this message in error, please delete it and immediately notify the sender by e-mail. Any use other than its intended purpose, dissemination or disclosure, either whole or partial, is prohibited except if formal approval is granted. As communication on the Internet is not secure, the sender does not accept responsibility for the content of this message.
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