Le 23/12/2010 14:14, Sylvere Teissier a écrit :
On 23/12/2010 12:59, Jean-Christophe Le Lann wrote:
Hello
We see that at cycle 20 address=0 is generated. ok.
One cycle later (21), I expected to get the data 85 (as in the
waveform), but here the message says 89.
Where am I wrong ?
You set the address at cycle 20
the address is latched by the synchronous memory at cycle 21
the output data is available on "dout" at "cycle 21 + t(access_time)"
so you read it only at cycle 22
Hi Sylvere
As the design is purely synchronous, the t(access_time) is 0. The
testbench process should see the dout at 21, no ?
Or a new question : setting the address at cycle 20, how could I read
the data at cycle 21 in the testbench process ?
JCLL
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