Sylvere Teissier wrote:
> Le 19/07/2011 21:52, Svenn Are Bjerkem a écrit :
>> I can, of course, add some buses up to top level and then achieve my
>> goal, but if vpi can save me from modifying the design, it would be a
>> better solution.
I my view simplest solution is to define a record type with all signals
to be monitored and add a single port with this record type. This way
one can add later as many signals to monitor as one wants without touching
the wiring in intermediate layers anymore. I have added such MONITOR or
DEBUG ports to many entities, and they are quite useful for testing, in
simulation as well in FPGAs.
> you can use a global signal probe
I agree, package global signal are a potential solution. This still has two
draw backs:
1. it is intrusive, the DUT must be modified
2. it only works for entities which are instantiated only once
With best regards, Walter
> see here:
> https://mail.gna.org/public/ghdl-discuss/2011-02/msg00032.html
>
> you have to slightly modify the design, but it doesn't affect synthesis
>
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