Hello, My colleagues and I love the new parameter -gNAME=VALUE to launch a simulation with some particular generics. It's very handy to evaluate and test entities in various situations. Thank you for that feature!
Currently the only handled generic type is string. While it's possible to convert this into any other type and value including integer/natural, it's not straightformard and this needs specific conversion functions. The code involved adds unnecessary complexity and tends to obfuscate functionality for people who don't know/understand where that comes from. See the little testbench I sent in previous messages as illustration (attached again there). Would it be possible to extend the feature to other generic types? I think std_logic and integer/natural/positive would fit most use cases. The conversion errors could then be properly detected by the simulator itself, which would add reliability to the test environment. Best regards, Adrien
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity phonybench is generic ( GENSTR : string := "adrien"; GENSTDLV : std_logic_vector(5 downto 0) := "111000"; GENSTDL : std_logic := '1'; GENNAT : natural := 22 ); end phonybench; architecture bench of phonybench is type char2std_t is array(character) of std_ulogic; constant char2std_c : char2std_t := ( 'U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'X' ); function str2std(arg : string) return std_logic_vector is variable result : std_logic_vector(arg'length - 1 downto 0); variable j : integer; begin j := arg'length - 1; for i in arg'range loop result(j) := char2std_c(arg(i)); j := j - 1; end loop; return result; end function; signal sigvec1 : std_logic_vector(5 downto 0) := str2std(GENSTR); signal sigvec2 : std_logic_vector(5 downto 0) := GENSTDLV; signal siglog : std_logic := GENSTDL; signal signat : natural := GENNAT; signal clk : std_logic := '0'; begin clk <= not clk after 5 ms; sigvec1 <= str2std(GENSTR); sigvec2 <= GENSTDLV; siglog <= GENSTDL; signat <= GENNAT; end architecture;
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