Hi, I'm a novice to GHDL and I have a few questions.
My goal is to read a VHDL file and translate component declarations of a certain type into plain assignments. I would also like to analyse the connectivity of these components and perform operations on these components depending on the connectivity between the components. I can achieve my goal with an AST, which I assume is generated in GHDL. My first question is: can GHDL help me achieve my goal? If so, can someone provide some references or steps on how to achieve this? Or is there a better approach or tool that can help me achieve my goal? I downloaded the source from the svn repository, and I was unable to compile the tool. I found some instruction in the README file in the translate folder, however I had no success. I am running Ubuntu 12.04 64 bit with an Intel ISA (i5). I have gcc 4.6.3 installed. Please let me know how to compile the tool. Also, an explanation on the directory hierarchy would be great. I assume the translate folder is where the majority of the code resides, since the other folders contain ads and adb that seem to be vhdl libraries. Nonetheless, your help would be appreciated to clarify the structure. Also, just a note that this work is for academic research. Thank you in advance, -- Vincent Mirian PhD Candidate Electrical and Computer Engineering University of Toronto Eco-Tip: Save trees! Do you really need to print this email? ;-)
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