Hi everybody, I've launched simulation of more than 12 (personal) VHDL designs, with GHDL, Xilinx's ISim from ISE Design Suite 2013.1 (full) and with Xilinx's XSim from Vivado Design Suite 2015.1 (full).
My initial goal was to find how much slower GHDL was compared to these commercial simulators. Note: I compiled GHDL against gcc 4.9 with isl, cloog, lto. Not tested without. My PC is 64 bits ArchLinux. I got a very nice surprise: all simulations were at least 2 times faster, sometimes 4 times faster, than ISim and XSim. For a design with an extreme density of generate statements, with even some recursive component instantiation, XSim did spend 10-15 minutes analyzing the "data flow" during elaboration. The generated simulator did the simulation in ~8 minutes. That design was elaborated in 20 seconds by GHDL, and the simulation took only 3 minutes :-) The only step done slower by GHDL is analysis, because it is not multithreaded. But that has a rather low importance. Anybody can do some comparison with Altera tool or Modelsim? Regards, Adrien _______________________________________________ Ghdl-discuss mailing list [email protected] https://mail.gna.org/listinfo/ghdl-discuss
