The quick measurements are overall times:
0) a bash or PowerShell wrapper script to launch the python program (different
platforms (Windows / Linux) need different environments and preparations)
1) a Python script that
- evaluates the command line arguments
- translates a generic file list into proprietary file lists or command
lists for the simulators (*.tcl scripts or *.prj files)
- assembles the argument lists to launch the simulators
2) compiling the sources
- iSim => fuse.exe
- xSim => xelab.exe
- vSim => calling vcom and vlib
- GHDL => calling ghdl -a
3) launching the simulation in batch / command line mode
- iSim/xSim => calling <testbench>.exe
- vSim => launching vsim
- GHDL => calling ghdl -r
The Windows version of GHDL has no explicit elaboration step. So -r includes -e.
So the time consists of preparation, compiling and simulation. If needed, it's
also possible to run all testbenches in GUI mode :).
Regards
Patrick
-----------------------------------
Wissenschaftliche Hilfskraft
Technische Universität Dresden
Fakultät Informatik
Institut für Technische Informatik
Lehrstuhl VLSI-Entwurfssysteme, Diagnostik und Architektur
01062 Dresden
Tel.: +49 351 463-38451
Fax: +49 351 463-38324
Raum: APB-1020
E-Mail: [email protected]
WWW: http://vlsi-eda.inf.tu-dresden.de
-----Original Message-----
From: Ghdl-discuss [mailto:[email protected]] On Behalf Of Adrien
Prost-Boucle
Sent: Thursday, August 06, 2015 10:02 PM
To: GHDL discuss list <[email protected]>
Subject: Re: [Ghdl-discuss] Simulation speed compared to ISim, XSim: GHDL shines
Hi,
I used gcc version of GHDL.
In attached text file you will find much more details about times and run
config.
Also attached is an archive containing some of the VHDL code I used.
It is 390kB, I hope the mailing list will let it pass.
Please don't try to understand any of it: I generated these with HLS tool AUGH
that I am developing and these were runs with silly test parameters.
@Patrick:
Can you indicate what are the times you provide?
- only simulation time ?
- analysis + elabo + simu ?
Regards,
Adrien
On Thu, 2015-08-06 at 15:34 -0400, Pascal Giard wrote:
> Hi Adrien and Patrick,
> are your results for the gcc, mcode or llvm backend?
>
> -Pascal
>
> On Thu, Aug 6, 2015 at 3:09 PM, Lehmann, Patrick
> <[email protected]> wrote:
> > Hello Adrien,
> >
> > I'm one of the developers of the PoC-Library. =>
> > https://github.com/VLSI-EDA/PoC This library comes with a set of
> > testbenches and some Python tools to abstract the simulation runs
> > for different simulators.
> >
> > Currently we support:
> > - iSim (14.7)
> > - xSim (2014.x/2015.x)
> > - GHDL (+GTKwave as viewer) and
> > - vSim (QuestaSim - tested with 10.2c)
> >
> > I used PoC's simple "arith_prefix_and" module from
> > "src/arith/arith_prefix_and.vhdl". It builds a carry-chain based AND
> > gate.
> > The implementation used Xilinx's XORCY and MUXCY primitives.
> >
> > arith_prefix_and: Number of input bits = 8:
> > iSim: 3.7574 sec
> > xSim: 3.1700 sec
> > vSim: 3.3036 sec
> > ghdl: 1.0233 sec
> >
> > A second more expensive example is a wide-adder (arith_addw.vhdl).
> > This adder is designed for wide inputs. The testbench uses only a
> > few bits to reduce runtime.
> >
> > arith_addw: Number of input bits = 9
> > iSim: 92.7182 sec
> > ghdl: 71.2711 sec
> > vSim: 38.4598 sec
> > xSim: 27.4511 sec
> >
> > So in my opinion: Yes, ghdl is mostly faster than iSim and xSim.
> > Especially the compiling part is much faster. While iSim/xSim and
> > vSim search the files and check them, ghdl is already simulating :).
> >
> > Regards
> > Patrick
> >
> > -----------------------------------
> > Wissenschaftliche Hilfskraft
> >
> > Technische Universität Dresden
> > Fakultät Informatik
> > Institut für Technische Informatik
> > Lehrstuhl VLSI-Entwurfssysteme, Diagnostik und Architektur
> > 01062 Dresden
> > Tel.: +49 351 463-38451
> > Fax: +49 351 463-38324
> > Raum: APB-1020
> > E-Mail: [email protected]
> > WWW: http://vlsi-eda.inf.tu-dresden.de
> >
> > -----Original Message-----
> > From: Ghdl-discuss [mailto:[email protected]] On Behalf
> > Of Adrien Prost-Boucle
> > Sent: Thursday, August 06, 2015 8:26 PM
> > To: GHDL discuss list <[email protected]>
> > Subject: [Ghdl-discuss] Simulation speed compared to ISim, XSim:
> > GHDL shines
> >
> > Hi everybody,
> >
> > I've launched simulation of more than 12 (personal) VHDL designs,
> > with GHDL, Xilinx's ISim from ISE Design Suite 2013.1 (full) and
> > with Xilinx's XSim from Vivado Design Suite 2015.1 (full).
> >
> > My initial goal was to find how much slower GHDL was compared to
> > these commercial simulators.
> > Note: I compiled GHDL against gcc 4.9 with isl, cloog, lto. Not
> > tested without. My PC is 64 bits ArchLinux.
> >
> > I got a very nice surprise: all simulations were at least 2 times
> > faster, sometimes 4 times faster, than ISim and XSim.
> >
> > For a design with an extreme density of generate statements, with
> > even some recursive component instantiation, XSim did spend 10-15
> > minutes analyzing the "data flow" during elaboration. The generated
> > simulator did the simulation in ~8 minutes.
> > That design was elaborated in 20 seconds by GHDL, and the simulation
> > took only 3 minutes :-)
> >
> > The only step done slower by GHDL is analysis, because it is not
> > multithreaded. But that has a rather low importance.
> >
> > Anybody can do some comparison with Altera tool or Modelsim?
> >
> > Regards,
> > Adrien
> >
> >
> > _______________________________________________
> > Ghdl-discuss mailing list
> > [email protected]
> > https://mail.gna.org/listinfo/ghdl-discuss
> >
> > _______________________________________________
> > Ghdl-discuss mailing list
> > [email protected]
> > https://mail.gna.org/listinfo/ghdl-discuss
> >
>
>
>
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