Hi All!
Last year the first free software tool chain for FPGAs emerged. The
IceStorm (http://www.clifford.at/icestorm/) project allows synthesis
from Verilog for Lattice iCE40 FPGAs.
This tool-chain uses Yosys (http://www.clifford.at/yosys/) as base.
But no VHDL. Recently Yodl (https://github.com/forflo/yodl) emerged.
Yodl is an effort to do what Yosys does for Verilog, but for VHDL.
I'm a complete ignorant about GHDL, Yosys and Yodl internals, but I'm
curious about the synergy between GHDL and Yodl.
I know GHDL is ADA code and I see Yodl is C++. But I see Yodl people
having some problems (or doubts) about the VHDL parser.
Just wondering ...
Regards, Salvador
P.D: I know IceStorm currently support
http://www.edautils.com/vhdl2verilog.html and this is an incomplete
solution.
--
Ing. Salvador Eduardo Tropea http://utic.inti.gob.ar/
INTI - Micro y Nanoelectrónica (CMNB) http://www.inti.gob.ar/
Unidad Técnica Sistemas Inteligentes Av. General Paz 5445
Tel: (+54 11) 4724 6300 ext. 6919 San Martín - B1650KNA
FAX: (+54 11) 4754 5194 Buenos Aires * Argentina
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