Le 2016-10-03 20:09, Adrien Prost-Boucle a écrit :
Hi,
Synthesis and simulation are indeed completely different things.
<snip>
Even if you consider that as the "simplest" part, it's still a big
part, and any reuse of good stuff would saves a lot of
reinvent-the-wheel time and allow to better focus on the the rest.
Regards,
Adrien
Let's think again about an idea I suggested, probably in 2009...
GHDL is a VHDL compiler.
Let's create a pseudo-machine target where the generated code
can be simulated, when run by a virtual machine, which will also
tag data as they pass throught function, ports etc.
A few runs will "discover", or simply "cover" all the datapaths
and thus create a directed dependency graph, which can be then
traced back from the outputs.
There, you have a synthesiser which would seamlessly integrate
with the best open source VHDL simulator.
yg
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