Are we talking about something like what yosys does for verilog? If so, have the work of Tim Edwards in memory: http://www.opencircuitdesign.com/qflow/index.html Alliance and Coriolis efforts from https://soc-extras.lip6.fr/en/alliance-abstract-en/ Mostly ASIC related backend stuff, but FPGA most likely needs to be routed by the proprietary tools. I guess mapping to FPGA can be done by FOSS tools if there is a logic library available.
-- Svenn _______________________________________________ Ghdl-discuss mailing list Ghdl-discuss@gna.org https://mail.gna.org/listinfo/ghdl-discuss
