So, I thought that since the Verilog ctags parser already supports both Verilog and SystemVerilog, it would be a matter of enabling the latter within Geany. But I'm currently stuck at creating a proper tag map in tm_parser.c - I didn't consider that tags have *meaning*.
I understood that tag categories were named mostly for convenience, but apparently the behavior of something marked as `tm_tag_variable_t` is not the same as that of something marked `tm_tag_local_var_t`, for example. And now, the problem is that SystemVerilog is not a "programming language" but a hardware description language, so trying to figure out how a "port" or a "module" maps to a set of tags intended for programming is complicated. If this were a matter of "getting creative" and assigning the tags randomly, that'd be done, but apparently I need to be careful because assigning one tag or another will result in different propagation rules, showing up or not on the left panel, etc. For the time being I created a draft PR so I can discuss it further. (Right now, there is a commit that does the SV integration, but the result is little more than what I would have gotten by adding a bunch of keywords to the filetypes.systemverilog file. The second commit attempts to do the right thing but it's still a WIP.) -- Reply to this email directly or view it on GitHub: https://github.com/geany/geany/pull/4039#issuecomment-2466834740 You are receiving this because you are subscribed to this thread. Message ID: <geany/geany/pull/4039/[email protected]>
