@techee requested changes on this pull request.
> @@ -195,6 +195,7 @@ static void init_builtin_filetypes(void)
FT_INIT( NIM, NONE, "Nim", NULL,
SOURCE_FILE, COMPILED );
FT_INIT( ZIG, NONE, "Zig", NULL,
SOURCE_FILE, COMPILED );
FT_INIT( DART, NONE, "Dart", NULL,
SOURCE_FILE, COMPILED );
+ FT_INIT( SYSVERILOG, SYSVERILOG, "SystemVerilog", NULL,
SOURCE_FILE, COMPILED );
Remove.
> @@ -115,6 +115,7 @@ typedef enum
GEANY_FILETYPES_NIM,
GEANY_FILETYPES_ZIG,
GEANY_FILETYPES_DART,
+ GEANY_FILETYPES_SYSVERILOG,
Remove.
> @@ -1057,6 +1057,7 @@ void highlighting_init_styles(guint filetype_idx,
> GKeyFile *config, GKeyFile *co
init_styleset_case(TXT2TAGS);
init_styleset_case(VHDL);
init_styleset_case(VERILOG);
+ init_styleset_case(SYSVERILOG);
Remove.
> @@ -1155,6 +1156,7 @@ void highlighting_set_styles(ScintillaObject *sci,
> GeanyFiletype *ft)
styleset_case(TXT2TAGS);
styleset_case(VHDL);
styleset_case(VERILOG);
+ styleset_case(SYSVERILOG);
Remove.
> @@ -1896,6 +1896,13 @@ static const HLKeyword highlighting_keywords_VERILOG[]
> =
#define highlighting_properties_VERILOG EMPTY_PROPERTIES
+/* SystemVerilog */
+#define highlighting_lexer_SYSVERILOG highlighting_lexer_VERILOG
+#define highlighting_styles_SYSVERILOG highlighting_styles_VERILOG
+#define highlighting_keywords_SYSVERILOG highlighting_keywords_VERILOG
+#define highlighting_properties_SYSVERILOG highlighting_properties_VERILOG
+
+
Remove.
> @@ -0,0 +1,62 @@
+# For complete documentation of this file, please see Geany's main
documentation
I don't think SystemVerilog should be implemented as a builtin filetype. Have a
look at e.g. `filetypes.JSON.conf` how to add a non-builtin filetype. Under the
`[settings]` section, add `tag_parser=SystemVerilog` and
`lexer_filetype=verilog`.
Rename this file to `filetypes.Systemverilog.conf` so it becomes a non-builtin
filetype
> @@ -120,6 +120,7 @@ enum
TM_PARSER_TXT2TAGS,
TM_PARSER_ABC,
TM_PARSER_VERILOG,
+ TM_PARSER_SYSVERILOG,
This should be moved to the end of the array so it doesn't break ABI.
> @@ -1257,6 +1315,7 @@ static TMParserMap parser_map[] = {
MAP_ENTRY(TXT2TAGS),
MAP_ENTRY(ABC),
MAP_ENTRY(VERILOG),
+ MAP_ENTRY(SYSVERILOG),
Move to the end, see below.
> @@ -55,6 +55,7 @@
Txt2tagsParser, \
AbcParser, \
VerilogParser, \
+ SystemVerilogParser, \
Move to the end of the array.
> @@ -76,11 +76,12 @@
> Sh=*.sh;configure;configure.in;configure.in.in;configure.ac;*.ksh;*.mksh;*.zsh;*
Smalltalk=*.st;
SQL=*.sql;
Swift=*.swift;
+SystemVerilog=*.sv;*.svh;
Add `SystemVerilog` to the `[Groups]` below under `Programming`.
> @@ -0,0 +1,62 @@
+# For complete documentation of this file, please see Geany's main
documentation
+[styling]
Replace with `[styling=Verilog]` and remove the rest of the section.
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